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data sheet v1.1 2009-04 microcontrollers 32-bit TC1797 32-bit single-chip microcontroller www.datasheet.co.kr datasheet pdf - http://www..net/
edition 2009-04 published by infineon technologies ag 81726 munich, germany ? 2009 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infin eon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warr anties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet v1.1 2009-04 microcontrollers 32-bit TC1797 32-bit single-chip microcontroller www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 data sheet v1.1, 2009-04 trademarks tricore? is a trademark of infineon technologies ag. TC1797 data sheet revision history: v1.1, 2009-04 previous version: v1.0, 2009-01 page subjects (major chan ges since last revision) page 1-4 typo of ttcan-related text is delet ed from the multican features. page 1-6 description is added for th e derivatives of TC1797. page 2-23 text which describes the endurance of pflash and dfla sh is enhanced. page 2-56 typo of big-endian support is deleted from the ebu section. page 5-133 the spike-filters parameters are included, t sf1 , t sf2 . page 5-137 the maximum limit for i oz1 is updated. page 5-145 the temperature sensor measurement time parameter is added. page 5-153 the condition for hwcfg is deleted from hold time from porst rising edge. page 5-154 the power, pad, reset timing fi gure is updated. page 5-155 the notes under the pll and eray-pll sect ions are updated. page 5-158 the eray parameter, accumulated jitter at sysclk pin is added. page 5-180 the eray timing diag ram is corrected, repl aced reference of v dd with v ddp . page 5-171 footnote for t 12 and t 21 for ebu burst mode ac cess timing section is updated. page 5-171 footnote 2 is added for t 10 , footnote 5 is added for t 23 , t 24 t 25 and t 26 in ebu burst mode acce ss timing section. we listen to your comments any information within this do cument that you feel is wron g, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 table of contents data sheet 1 v1.1, 2009-04 table of contents 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 about this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 related documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 text conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 reserved, undefined, an d unimplemented terminology . . . . . . . . . . . . 9 2.1.4 register access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 abbreviations and ac ronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 system architecture of the tc1 797 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 TC1797 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 cpu cores of the TC1797 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3.1 high-performance 32-bit cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.3.2 high-performance 32-bit peripheral co ntrol processor . . . . . . . . . . . 17 2.3 on-chip system units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.1 flexible interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 direct memory access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.4 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4.1 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4.2 features of the watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4.3 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.4.4 external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.4.5 die temperature measuremen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.5 general purpose i/o ports and peripheral i/o lines . . . . . . . . . . . . . . . 23 2.3.6 program memory unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.6.1 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.6.2 overlay ram and data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.6.3 emulation memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.6.4 tuning protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.6.5 program and data flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.7 data access overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.5 on-chip peripheral units of th e TC1797 . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5.1 asynchronous/synchronous seri al interfaces . . . . . . . . . . . . . . . . . . . . 33 2.5.2 high-speed synchronous seri al interfaces . . . . . . . . . . . . . . . . . . . . . . 35 2.5.3 micro second channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5.4 flexray? protocol controller (e-ray) . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.5.4.1 e-ray kernel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.5.4.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 table of contents data sheet 2 v1.1, 2009-04 2.5.5 multican controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.6 micro link serial bus interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.7 general purpose timer array (gpta) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.5.7.1 functionality of gpta0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.5.7.2 functionality of ltca2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.5.8 analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.8.1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.8.2 fadc short description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.5.9 external bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.6 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.6.1 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.2 real time trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.3 calibration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.4 tool interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.6.5 self-test support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.6.6 far support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1 TC1797 pin definition and functions: p/pg -bga-416-10 . . . . . . . . . . . . 60 3.1.1 TC1797 p/pg-bga-416-1 0 package variant pin conf iguration . . . . . . 61 3.1.2 pull-up/pull-down re set behavior of the pi ns . . . . . . . . . . . . . . . . . . 122 4 identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.1.2 pad driver and pad classe s summary . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2.2 analog to digital converters (adc0/adc1 /adc2) . . . . . . . . . . . . . . . 137 5.2.3 fast analog to digital converter (fadc) . . . . . . . . . . . . . . . . . . . . . . . 142 5.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.2.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3.2 output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.4 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.5 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.3.6 e-ray phase locked loop (e -ray pll) . . . . . . . . . . . . . . . . . . . . . . . 158 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 table of contents data sheet 3 v1.1, 2009-04 5.3.7 bfclko output clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.8 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.3.9 dap interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.10 ebu timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.10.1 ebu asynchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.10.2 ebu burst mode access ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.10.3 ebu arbitration signal timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.3.11 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.11.1 micro link interface (mli) timing . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.11.2 micro second ch annel (msc) interface timing . . . . . . . . . . . . . . . 177 5.3.11.3 ssc master/slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.3.11.4 e-ray interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4 package and reliabi lity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.4.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 5.4.4 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 summary of features data sheet 4 v1.1, 2009-04 1 summary of features ? high-performance 32-bit su per-scalar tricore v1.3.1 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 180 or 150 1) mhz operation at full temperature range ? 32-bit peripheral control processor with single cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? 180 or150 1) mhz operation at full temperature range ? multiple on-chip memories ?4 or 3 1) mbyte program flash memo ry (pflash) with ecc ? 64 kbyte data flash memory (dfla sh) usable for eeprom emulation ? 128 kbyte data memory (ldram) ? 40 kbyte code scratc hpad memory (spram) ? instruction cache: up to 16 kbyte (icache, configurable) ? data cache: up to 4 kbyte (dcache, configurable) ? 8 kbyte overlay memory (ovram) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? 32-bit external bus in terface unit (ebu) with ? 32-bit demultiplexed / 16-b it multiplexed external bu s interface (3.3v, 2.5v) ? support for burst flash memory devices ? scalable external bus timing up to 75 mhz ? sophisticated interrupt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? 64-bit local memory buses betwee n cpu, ebu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip periph eral and func tional units ? one bus bridges (lfi bridge) ? versatile on-chip peripheral units ? two asynchronous/synchrono us serial channels (asc) with baud rate generator, parity, framing and ov errun error detection ? two high-speed synchronous serial ch annels (ssc) with pr ogrammable data length and shift direction ? two serial micro second bu s interface (msc) for serial port expansion to external power devices 1) derivative dependent. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 summary of features data sheet 5 v1.1, 2009-04 ? two high-speed micro li nk interface (mli) for serial inter-processor communication ? one multican module with 4 can n odes and 128 free a ssignable message objects for high efficiency data handling via fifo buffering and gateway data transfer ? one flexray tm module with 2 channels (e-ray). ? two general purpose time r array modules (gpta) wi th additional local timer cell array (ltca2) providing a powerful se t of digital signal filtering and timer functionality to realiz e autonomous and complex input/out put management ? 44 analog input lines for adc ? 3 independent kernel s (adc0, adc1, adc2) ? analog supply voltage range from 3.3 v to 5 v (single supply) ? performance for 12 bit resolution (@f adci = 10 mhz) ? 4 different fadc input channels ? channels with impedan ce control and overla id with adc1 inputs ? extreme fast conversion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz) ? 10-bit a/d conversion (h igher resolution can be achieved by averaging of consecutive conversions in di gital data reduction filter) ? 221 digital general purpose i/o lines 1) (gpio), 4 input lines ? digital i/o ports with 3.3 v capability ? on-chip debug support fo r ocds level 1 (cpu, pc p, dma, on chip bus) ? dedicated emulatio n device chip av ailable (TC1797ed) ? multi-core debugging, real ti me tracing, and calibration ? four/five wire jtag (ieee 1149.1) or two wire dap (device access port) interface ? power management system ? clock generation unit with pll ? core supply voltage of 1.5 v ? i/o voltage of 3.3 v ? full automotive temperatur e range: -40 to +125c ? package variants: p/pg-bga-416-10 1) TC1797 package variant p/pg-bga-416-10: 86 gpios www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 summary of features data sheet 6 v1.1, 2009-04 ordering information the ordering code for infineo n microcontrollers provides an exact reference to the required product. this or dering code identifies: ? the derivative itself, i.e. its function se t, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes fo r the TC1797 please refer to the ?product catalog microcontrollers? , which summarizes all availabl e microcontroller variants. this document descri bes the derivatives of the device.the table 1 enumerates these derivatives and summari zes the differences. table 1 TC1797 derivative synopsis derivative ambient temperature range program flash cpu frequency sak-TC1797-512f180e t a = -40 o c to +125 o c 4 mbytes 180mhz sak-TC1797-384f150e t a = -40 o c to +125 o c 3 mbytes 150mhz www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 7 v1.1, 2009-04 2 introduction this data sheet describes th e infineon TC1797, a 32-bit microcontrol ler dsp, based on the infineon tricore architecture. 2.1 about this document this document is designed to be read primarily by design engineers and software engineers who need a detailed description of the interactions of the TC1797 functional units, registers, instru ctions, and exceptions. this TC1797 data s heet describes the features of th e TC1797 with respect to the tricore architecture. where the TC1797 di rectly implements tr icore architectural functions, this manual simply refers to those func tions as features of the TC1797. in all cases where this manual describes a TC1797 feature without refe rring to the tricore architecture, this means that the TC1797 is a direct impl ementation of the tricore architecture. where the TC1797 implem ents a subset of tr icore architectural fe atures, this manual describes the TC1797 im plementation, and then describes how it differs from the tricore architecture. such di fferences between the TC1797 and the tricor e architecture are documented in the section covering each su ch subject. 2.1.1 related documentations a complete description of t he tricore architecture is fo und in the docu ment entitled ?tricore architecture manual?. the architecture of the tc 1797 is described separately this way because of the configurable nature of the tricore specification: different versions of the architecture may contain a different mix of systems components. the tricore architecture, however, remains constant across all derivative designs in order to preserve compatibility. this data sheets together wi th the ?tricore architectu re manual? are required to understand the comple te TC1797 micro cont roller functionality. 2.1.2 text conventions this document uses the fo llowing text conventions fo r named components of the TC1797: ? functional units of the tc17 97 are given in plain upper case. for example: ?the ssc supports full- duplex and half-duplex sy nchronous communication?. ? pins using negative logic are indicated by an overline. for exam ple: ?the external reset pin, esr0 , has a dual function.?. ? bit fields and bits in register s are in general referenced as ?module_register name.bit field? or ?m odule_register name.bit?. for example: ?the current cpu priority number bit field cpu_icr.ccpn is cleared?. most of the www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 8 v1.1, 2009-04 register names contain a modu le name prefix, separated by an underscore character ?_? from the actual register name (for example, ?asc0_ con?, where ?asc0? is the module name prefix, and ?con? is the kernel register name ). in chapters describing the kernels of the peripheral modules, the registers are ma inly referenced with their kernel register names. the peripheral module implementati on sections mainly refer to the actual register nam es with module prefixes. ? variables used to describe sets of processing units or registers appear in mixed upper and lower cases. for example, register name ?msg cfgn? refers to multiple ?msgcfg? registers with variable n. th e bounds of the variabl es are always given where the register expression is first used (for example, ?n = 0-31?), and are repeated as needed in the rest of the text. ? the default radix is decimal. hexadecimal constants are suffixed with a subscript letter ?h?, as in 100 h . binary constants are suffixed with a subscript letter ?b?, as in: 111 b . ? when the extent of register fields, groups register bits , or groups of pins are collectively named in t he body of the document, they are represented as ?name[a:b]?, which defines a range for the named group from b to a. individual bits, signals, or pins are given as ?name[c]? where the range of the variable c is given in the text. for example: cfg[2:0] and srpn[0]. ? units are abbreviated as follows: ? mhz = megahertz ? s = microseconds ? kbaud, kbit = 1000 characters /bits per second ? mbaud, mbit = 1,000,000 charac ters/bits per second ? kbyte, kb = 1024 bytes of memory ? mbyte, mb = 1048576 bytes of memory in general, the k prefix scal es a unit by 1000 whereas th e k prefix scales a unit by 1024. hence, the kbyte unit scales the expression pr eceding it by 1024. the kbaud unit scales the expres sion preceding it by 1000 . the m prefix scales by 1,000,000 or 1048576, and scales by .00000 1. for example, 1 kbyte is 1024 bytes, 1 mbyte is 1024 1024 bytes, 1 kbaud/kbit are 1000 characters/bits per second, 1 mbaud/mbit are 1000000 charac ters/bits per second, and 1 mhz is 1,000,000 hz. ? data format quantities are defined as follows: ? byte = 8-bit quantity ? half-word = 16-bit quantity ? word = 32-bit quantity ? double-word = 64-bit quantity www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 9 v1.1, 2009-04 2.1.3 reserved, undefined, and unimplemented terminology in tables where regist er bit fields are defi ned, the following co nventions are used to indicate undefined and unimplemented functi on. furthermore, types of bits and bit fields are defined using the abbre viations as shown in table 2 . 2.1.4 register access modes read and write access to regi sters and memory locations ar e sometimes restricted. in memory and register access ta bles, the terms as defined in table 3 are used. table 2 bit function terminology function of bits description unimplemented, reserved register bit fields named 0 indicate unimplemented functions with the following behavior. ? reading these bit fields returns 0. ? these bit fields should be written with 0 if the bit field is defined as r or rh. ? these bit fields have to be written with 0 if the bit field is defined as rw. these bit fields are reserved. th e detailed descri ption of these bit fields can be found in the register descriptions. rw the bit or bit field ca n be read and written. rwh as rw, but bit or bit field can be also set or reset by hardware. r the bit or bit field can only be read (read-only). w the bit or bit field can only be wri tten (write-only). a read to this register will always give a default value back. rh this bit or bit field can be modified by hardware (read-hardware, typical example: status flags). a r ead of this bit or bit field give the actual status of this bit or bit field back. writing to this bit or bit field has no effect to the se tting of this bit or bit field. s bits with this attribut e are ?sticky? in one di rection. if their reset value is once overwr itten by software, th ey can be switched again into their reset state only by a reset operat ion. software cannot switch this type of bit into its rese t state by writing the register. this attribute can be combined to ?rws? or ?rwhs?. f bits with this attribute are readab le only when they are accessed by an instruction fetch. normal data read operat ions will return other values. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 10 v1.1, 2009-04 2.1.5 abbreviations and acronyms the following acronyms and term s are used in this document: table 3 access terms symbol description u access mode: access permi tted in user mode 0 or 1. reset value: value or bit is no t changed by a reset operation. sv access permitted in supervisor mode. r read-only register. 32 only 32-bit word accesses are permi tted to this regi ster/address range. e endinit-protected register/address. pw password-protected register/address. nc no change, indicated re gister is not changed. be indicates that an access to this address range gene rates a bus error. nbe indicates that no bus error is gener ated when accessing this address range, even though it is either an ac cess to an undefined address or the access does not follow the given rules. ne indicates that no error is generat ed when accessing this address or address range, even thoug h the access is to an undefined address or address range. true for cpu access es (mtcr/mfcr) to undefined addresses in the csfr range. adc analog-to-digital converter agpr address general purpose register alu arithmetic and logic unit asc asynchronous/synchronous serial controller bcu bus control unit brom boot rom & test rom can controller area network cmem pcp code memory cisc complex instructio n set computing cps cpu slave interface cpu central processing unit www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 11 v1.1, 2009-04 csa context save area csfr core special function register dap device access port das device access server dcache data cache dflash data flash memory dgpr data general purpose register dma direct memory access dmi data memory interface ebu external bus interface emi electro-magnetic interference fadc fast analog-to-digital converter fam flash array module fcs flash command state machine fim flash interface and control module fpi flexible peripheral interconnect (bus) fpu floating point unit gpio general purpos e input/output gpr general purpose register gpta general purpose timer array icache instruction cache i/o input / output jtag joint test action group = ieee1149.1 lbcu local memory bus control unit ldram local data ram lfi local memory-to-fpi bus interface lmb local memory bus ltc local timer cell mli micro link interface mmu memory management unit msb most significant bit msc micro second channel www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 12 v1.1, 2009-04 nc not connected nmi non-maskable interrupt ocds on-chip debug support ovram overlay memory pcp peripheral control processor pmu program memory unit pll phase locked loop pcode pcp code memory pflash program flash memory pmi program memory interface pmu program memory unit pram pcp parameter ram ram random access memory risc reduced instructio n set computing sbcu system peripheral bus control unit scu system control unit sfr special function register spb system peripheral bus spram scratch-pad ram sram static data memory srn service request node ssc synchronous serial controller stm system timer wdt watchdog timer www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 13 v1.1, 2009-04 2.2 system architecture of the TC1797 the TC1797 combines three power ful technologies with in one silicon die, achieving new levels of power, sp eed, and economy for em bedded applications: ? reduced instruction set computing (risc) processor architecture ? digital signal processing (dsp) operations and addressing modes ? on-chip memories and peripherals dsp operations and addressing modes prov ide the computational power necessary to efficiently analyze complex real-world sign als. the risc load/store architecture provides high computational bandwidth wi th low system cost. on-chip memory and peripherals are designed to su pport even the most demanding high-ba ndwidth real-time embedded control-systems tasks. additional high-level featur es of the tc 1797 include: ? efficient memory organiza tion: instruction and data scratch memories, caches ? serial communication interfaces ? flexib le synchronous and asynchronous modes ? peripheral control processor ? standalone data operations and interrupt servicing ? dma controller ? dma operat ions and interrupt servicing ? general-purpose timers ? high-performance on-chip buses ? on-chip debugg ing and emulat ion facilities ? flexible interconnections to external components ? flexible power-management the TC1797 is a high-performan ce microcontroller with tricore cpu, program and data memories, buses, bus arbitratio n, an interrupt controller, a peripheral control processor and a dma controller and seve ral on-chip peripher als. the TC1797 is designed to meet the needs of the most dema nding embedded control syste ms applications where the competing issues of price/pe rformance, real-tim e responsiveness, computational power, data bandwidth, and po wer consumption are ke y design elements. the TC1797 offers several vers atile on-chip peripheral units su ch as serial controllers, timer units, and analog-to-digital converters . within the TC1797, all these peripheral units are connected to the tricore cpu/system via the flexible peri pheral interconnect (fpi) bus and the loca l memory bus (lmb). several i/o lines on the TC1797 ports are reserved for these peripheral units to communicate with the external world. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 14 v1.1, 2009-04 2.2.1 TC1797 block diagram figure 1 shows the block di agram of the TC1797. figure 1 TC1797 block diagram e-ray (2 channels) ebu ocds l1 debug interface/jtag mli0 mli1 memcheck fadc tricore cpu pmi 32 kb spram 8 kb icache interrupt system fpi-bus interface 16 kb pram pcp2 core 32 kb cmem interrupts system peripheral bus system peripheral bus (spb) ssc0 sbcu bridge dma 16 channels smif dmi ldram dcache cps bcu pmu0 gpta0 multi can (4 nodes, 128 mo) asc0 asc1 msc 0 (lvds) ssc1 stm scu ports 1.5v, 3.3v ext. supply ext. request unit gpta1 msc 1 (lvds) 2 mb pflash 64 kb dflash 8 kb ovram 16 kb brom 5 v ( 3 . 3 v s u p p o r t e d a s w e l l ) e x t . a d c s u p p l y adc0 adc1 16 blockdiagram TC1797 m m/s ltca2 local memory bus (lmb) 16 3 . 3 v e x t . f a d c s u p p l y 24 kb spram 16 kb icache (configurable) 124 kb ldram 4 kb dcache (configurable) fpu adc2 16 analog input assignment (hardwired/configurable) pll e-ray pll f e-ray f cpu abbreviations: icache: instruction cache dcache data cache spram: scratch-pad ram ldram: local data ram ovram: overlay ram brom: boot rom pflash: program flash dflash: data flash pram: parameter ram in pcp pcode: code ram in pcp 1 mb pflash pmu1 1 mb pflash 1) the upper mb of the pmu1 is available only in the 4mbyte derivative 1) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 15 v1.1, 2009-04 2.2.2 system features the TC1797 has the fo llowing features: package ? p/pg-bga-416-10 pa ckage, 1mm pitch clock frequencies for the 180 mhz derivative ? maximum cpu clock frequency: 180 mhz 1) ? maximum pcp clock frequency: 180 mhz 2) ? maximum system cl ock frequency: 90 mhz 3) clock frequencies for the 150 mhz derivative ? maximum cpu clock frequency: 150 mhz 1) ? maximum pcp clock frequency: 150 mhz 2) ? maximum system cl ock frequency: 90 mhz 3) 1) for cpu frequencies > 90 mhz, 2:1 mode has to be enabled. cpu 2:1 mode means: f fpi = 0.5 * f cpu 2) for pcp frequencies > 90 mhz, 2:1 mode has to be enabled. pcp 2:1 mode means: f fpi = 0.5 * f pcp 3) cpu 1:1 mode means: f fpi = f cpu . pcp 1:1 mode means: f fpi = f pcp www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 16 v1.1, 2009-04 2.2.3 cpu cores of the TC1797 the TC1797 includes a high performance cpu and a peri pheral control processor. 2.2.3.1 high-performance 32-bit cpu this chapter gives an overview about the tricore 1 architecture. tricore (tc1.3.1) arch itectural highlights ? unified risc mcu/dsp ? 32-bit architecture with 4 gbytes unified data, progra m, and input/output address space ? fast automatic context-switching ? multiply-accumulate unit ? floating point unit ? saturating integer arithmetic ? high-performance on-chip peripheral bus (fpi bus) ? register based design with mu ltiple variable register banks ? bit handling ? packed data operations ? zero overhead loop ? precise exceptions ? flexible power management high-efficiency tricore instruction set ? 16/32-bit instructions for reduced code size ? data types include: boolean, array of bi ts, character, signed and unsigned integer, integer with saturation, si gned fraction, double-word in tegers, and ieee-754 single- precision floating point ? data formats include: bit, 8-bi t byte, 16-bit half-word, 32-b it word, and 64-bit double- word data formats ? powerful instruction set ? flexible and efficient addressi ng mode for hi gh code density integrated cpu rela ted on-chip memories ? instruction memory: 40 kb total. after reset, configured into: 1) ?40 kbyte scratch-pad ram (spram) ?0 kbyte instructio n cache (icache) ? data memory: 128 kb total. after reset, configured into: 1) ? 128 kbyte local data ram (ldram) 1) software configurable. available options are described in the cpu chapter. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 17 v1.1, 2009-04 ?0 kbyte data cache (dache) ? on-chip srams with parity error detection 2.2.3.2 high-performance 32-bit pe ripheral control processor the pcp is a flexible perip heral control processor optimi zed for interrupt handling and thus unloading the cpu. features ? data move between any two memory or i/o locations ? data move until predef ined limit supported ? read-modify-write capabilities ? full computation capabilitie s including basic mul/div ? read/move data and accumulate it to previously read data ? read two data values and pe rform arithmetic or logica l operation and store result ? bit-handling capabilities (testing, setting, clearing) ? flow control instructions (conditional/unconditi onal jumps, breakpoint) ? dedicated interrupt system ? pcp srams with pa rity error detection ? pcp/fpi clock mode 1: 1 and 2:1 available integrated pcp related on-chip memories ?32 kbyte code memory (cmem) ?16 kbyte parameter memory (pram) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 18 v1.1, 2009-04 2.3 on-chip system units the TC1797 microcontroller o ffers several versatile on-ch ip system peripheral units such as dma controller, embedded flash modul e, interrupt syst em and ports. 2.3.1 flexible interrupt system the TC1797 includes a program mable interrupt system with the following features: features ? fast interrupt response ? independent interrupt systems for cpu and pcp ? each srn can be mapped to t he cpu or pcp interrupt system ? flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt system 2.3.2 direct memory access controller the TC1797 includes a fast and flexible dma contro ller with 16 independant dma channels (two dm a move engines). features ? 8 independent dma channels ? 8 dma channels in the dma sub-block ? up to 16 selectable reques t inputs per dma channel ? 2-level programmable pr iority of dma ch annels within the dma sub-block ? software and hard ware dma request ? hardware requests by selected on-c hip peripherals a nd external inputs ? 3-level programmable priority of the dm a sub-block at the on chip bus interfaces ? buffer capability for move ac tions on the buses (at least 1 move per bus is buffered) ? individually programmable opera tion modes for each dma channel ? single mode: stops an d disables dma channel after a predefined number of dma transfers ? continuous mode : dma channel remains enabled af ter a predefined number of dma transfers; dma transaction can be repeated ? programmable address modification ? two shadow register modes (with / w/o au tomatic re-set and direct write access). ? full 32-bit addressing ca pability of each dma channel ? 4 gbyte address range ? data block move supp orts > 32 kbyte moves per dma transaction ? circular buffer addressing mode wi th flexible circ ular buffer sizes ? programmable data width of dma transfer/transaction: 8-bit, 16-bit, or 32-bit ? register set for each dma channel www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 19 v1.1, 2009-04 ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt generatio n (the service request node lo gic for the mli channel is also implemented in the dma module) ? dma module is working on spb frequen cy, lmb interface on lmb frequency. ? dependant on the target/des tination address, read/write requests from the move engine are directed to the spb, lmb, mli or to the the cerberus. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 20 v1.1, 2009-04 2.3.3 system timer the TC1797?s stm is desi gned for global system timing app lications requiring both high precision and long range. features ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56 -bit counter can be read synchronously ? flexible interrupt generat ion based on compar e match with partial stm content ? driven by maxi mum 90 mhz (= f sys , default after reset = f sys /2) ? counting starts automatica lly after a re set operation ? stm registers are reset by an application reset if bit arst dis.stmdis is cleared. if bit arstdis.stmdis is se t, the stm is not reset. ? stm can be halted in debug/suspend mode special stm register semantics provide synchronous views of the entire 56-bit counter, or 32-bit subsets at differe nt levels of resolution. the maximum clock period is 2 56 f stm . at f stm = 90 mhz, for example, the stm counts 25.39 years before overflowing. t hus, it is capable of continuously timing the entire expected product life time of a system without overflowing. in case of a power-on reset, a watchdog reset, or a software reset, the stm is reset. after one of these reset conditions, the stm is e nabled and immediately st arts counting up. it is not possible to affect the content of th e timer during normal o peration of the TC1797. the stm can be optionally di sabled for power-saving purp oses, or suspended for debugging purposes via its clock contro l register. in suspen d mode of the TC1797 (initiated by writing an appropriate value to stm_cl c register), th e stm clock is stopped but all register s are still readable. due to the 56-bit width of the stm, it is not possible to read its entire content with one instruction. it needs to be read with two load instructions. since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the ti mer to the high part between the two read operatio ns). to enable a synchronous and consistent reading of the stm content, a capture r egister (stm_cap) is implemen ted. it latches the content of the high part of the stm each time when one of the registers stm_tim0 to stm_tim5 is read. thus, stm_cap holds the upper value of the timer at exactly the same time when the lower part is read. the second read operation would then read the content of the stm_cap to get the complete timer value. the content of the 56-bit sy stem timer can be compared against the content of two compare values stored in the stm_cmp0 and stm_cmp1 registers. interrupts can be generated on a compare ma tch of the stm with the stm_cmp0 or stm_cmp1 registers. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 21 v1.1, 2009-04 figure 2 provides an overview on the stm module. it shows the opti ons for reading parts of stm content. figure 2 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 56-bit system timer address decoder clock control mcb06185_mod compare register 0 interrupt control compare register1 porst stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 enable / disable f stm stm irq0 31 23 15 7 0 31 23 15 7 0 55 47 39 31 23 15 7 0 stm irq1 to dma etc. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 22 v1.1, 2009-04 2.3.4 system control unit the following scu introduction gives an overview about the TC1797 system control unit (scu) for information about the scu see chapter 3. 2.3.4.1 clock generation unit the clock generation unit (cgu) allows a very flexible clock generation for the TC1797. during user program executio n the frequency can be programmed for an optimal ratio between performance and power consumption. 2.3.4.2 features of the watchdog timer the main features of th e wdt are summarized here. ? 16-bit watchdog counter ? selectable input frequency: f fpi /256 or f fpi /16384 ? 16-bit user-definable reload value for normal wa tchdog operation, fi xed reload value for time-out and prewarning modes ? incorporation of the endinit bit and monitoring of its modifications ? sophisticated password a ccess mechanism with fixed and user-definable password fields ? access error detection: invalid password (d uring first access) or invalid guard bits (during second ac cess) trigger the watc hdog reset generation ? overflow error detection: an overflow of the counter triggers the watchdog reset generation ? watchdog function can be disa bled; access protection an d endinit monitor function remain enabled ? double reset detection 2.3.4.3 reset operation the following reset reques t triggers are available: ? 1 external power-o n hardware reset request trigger; porst , (cold reset) ? 2 external system r equest reset triggers; esr0 and esr1 ,(warm reset) ? watchdog timer (wdt ) reset request tri gger, (warm reset) ? software reset (sw), (warm reset) ? debug (ocds) reset reques t trigger, (warm reset) ? resets via the jtag interface there are two basic types of reset request triggers: ? trigger sources that do not de pend on a clock, such as the porst . this trigger force the device into an asynchronous reset assertion i ndependently of any clock. the activation of an asynchronous reset is as ynchronous to the sy stem clock, whereas its de-assertion is synchronized. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 23 v1.1, 2009-04 ? trigger sources that need a clock in order to be asserted, such as the input signals esr0 , esr1 , the wdt trigger, the parity trigger, or the sw trigger. 2.3.4.4 external interface the scu provides interface pad s for system purpose. variou s functions are covered by these pins. due to the differen t tasks some of the pads ca n not be shared with other functions but most of them c an be shared with ot her functions. the following functions are covered by the s cu controlled pads: ? reset request triggers ? reset indication ? trap request triggers ? interrupt request triggers ? non scu module triggers the first three points are covered by the esr pads and the last two points by the eru pads. 2.3.4.5 die temperature measurement the die temperature sensor (dts) generates a measuremen t result that indicates directly the current temperat ure. the result of the measurement ca n be read via an dts register. 2.3.5 general purpose i/o ports and peripheral i/o lines the TC1797 includes a flexible ports st ructure with the following features: features ? digital general-purpose inpu t/output (gpio) port lines ? input/output functionalit y individually programmab le for each port line ? programmable input char acteristics (pull-up, pul l-down, no pull device) ? programmable output driver strength for emi minimization (weak, medium, strong) ? programmable output characte ristics (push-pull, open drain) ? programmable alternat e output functions ? output lines of each port can be updated port-wise or set/reset/toggled bit-wise 2.3.6 program memory unit (pmu) the devices of the audof family contain at least one program memory unit. this is named ?pmu0?. some devices contain addi tional pmus which are named ?pmu1?, ? in the TC1797, the pmu0 contai ns the following submodules: ? the flash command and fetch control interface for prog ram flash and data flash. ? the overlay ram interface with online data acqu isition (olda) support. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 24 v1.1, 2009-04 ? the boot rom interface. ? the emulation memory interface. ? the local memory bus lmb slave interface. following memories ar e controlled by and belong to the pmu0: ?2 mbyte of program flash memory (pflash) ?64 kbyte of data flash memory (dflash, represents 16 kbyte eeprom) ?16 kbyte of boot rom (brom) ?8 kbyte overlay ram (ovram) in the TC1797 an addi tional pmu is incl uded with only a subset of pmu0?s submodules: ? the flash command and fetch control in terface but only for program flash. ? the local memory bus lmb slave interface. the following memories are contro lled and belong to the pmu1: ?2 mbyte of program flash memory (pflash). because of its indep endence from pmu0 this se cond pmu enab les additional functionality: re ad while write (rww), write while wr ite (www) or concurrent data and instruction accesses, if those are operati ng on different pmus. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 25 v1.1, 2009-04 the following figure shows th e block diagram of the pmu0: figure 3 pmu0 basic block diagram as described before the pmu1 is reduced to th e pflash and its controlling submodules. 2.3.6.1 boot rom the internal 16 kbyte boot rom (brom) is divi ded into two parts, used for: ? firmware (boot rom), and ? factory test routines (test rom). the different sections of the firmware in boot rom provide startup and boot operations after reset. the testrom is reserved for spec ial routines, which ar e used for testing, stressing and qualificat ion of the component. pmu0 pmu0_basicblockdiag _generic pmu control overlay ram interface emulation memory (ed chip only ) flash interface module dflash pflash 64 rom control brom 64 emulation memory interface ovram 64 to/from local memory bus lmb interface slave 64 64 64 64 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 26 v1.1, 2009-04 2.3.6.2 overlay ram and data acquisition the overlay memory ovram is provided in the pmu especial ly for redirection of data accesses to program memory to the ovra m by using the data ov erlay function. the data overlay functionality itself is controlled in the dmi module. for online data acqu isition (olda) of application or calibration data a virtual 32 kb memory range is provided wh ich can be accessed without error reporting. accesses to this olda range can also be redirected to an overlay memory. 2.3.6.3 emulation memory interface in TC1797 emulation device, an emulation me mory (emem) is provided, which can fully be used for calibration via program memory or olda over lay. the emulation memory interface shown in figure 0-1 is a 64-bit wide memory in terface that controls the cpu- accesses to the emulation memory in the TC1797 emul ation device. in the TC1797 production device, the emem in terface is always disabled. 2.3.6.4 tuning protection tuning protection is required by the user to absolute ly protect contro l data (e.g. for engine control), serial number and user software, stored in the flash, from being manipulated, and to safely de tect changed or disturbed da ta. for the internal flash, these protection requirements are excell ently fulfilled in the TC1797 with ? flash read and write prot ection with user-s pecific protection levels, and with ? dedicated hw and firmware, s upporting the internal flas h read protection, and with ? the alternate boot mode. special tuning protection supp ort is provided for external flash, which must also be protected. 2.3.6.5 program and data flash the embedded flash module s of pmu0 includes 2 mbyte of flash memory for code or constant data (called progra m flash) and additionally 64 kbyte of flash memory used for emulation of eeprom data (called data flash). the prog ram flash is realized as one independent fl ash bank, whereas the data flash is built of two flash banks, allowing the following combinations of concur rent flash operations: ? read code or data from prog ram flash, while one bank of data flas h is busy with a program or erase operation. ? read data from one bank of data flash, while the other bank of data flash is busy with a program or erase operation. ? program one bank of data flash while erasing the other bank of data flash, read from program flash. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 27 v1.1, 2009-04 in TC1797 the pmu1 contains 2 mbyte of program flash realiz ed as one flash bank. it does not contain any data flash. since in TC1797 the two pmus can work in parallel, further combinations of concurrent operations are supported if those are operat ing on flash modules in different pmus, e.g. ? read data from flas h1 while accessing code from flash0. ? read code or data from one flash while the other flash is busy with program or erase operation. ? both flash modules are concurrently bu sy with program or erase operation. both, the program flash and the data flash, provide error corre ction of single -bit errors within a 64-bit read double- word, resulting in an extrem ely low failure rate. read accesses to program flash are executed in 256-bit width, to data flash in 64-bit width (both plus ecc). single-cyc le burst transfers of up to 4 double-words and sequential prefetching with control of prefetch hit are supported fo r program flash. the minimum programming width is the page, including 256 bytes in program flash and 128 bytes in data flash. concurrent progra mming and erasing in data flash is performed using an automatic er ase suspend and resume function. a basic block diagram of th e flash module is shown in the following figure. figure 4 basic block diagram of flash module all flash operations are cont rolled simply by transferri ng command sequences to the flash which are based on jede c standard. this user inte rface of the embedded flash is very comfortable, becaus e all operations are controlled with high level commands, such as ?erase sector?. state transitions, such as terminat ion of command execution, or errors are reported to the user by ma skable interrupts. co mmand sequences are page write buffers 256 byte and 128 byte pf-read buffer 256 +32 bit and df-read buffer 64 +8 bit voltage control flash array module fam bank 0 program flash ecc block 8 ecc code wr_data rd_data flash interface&control module fim 64 64 64 64 read bus write bus flash command state machine fcs addr bus control fsi address control flash_basicblockdiagram _generic.vsd pmu bank 1 data flash bank 0 bank 1 flash fsi & array redundancy control sfrs fsram microcode 8 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 28 v1.1, 2009-04 normally written to flash by the cpu, but may also be issu ed by the dma controller (or ocds). the flash also features an adv anced read/write protection ar chitecture, including a read protection for the wh ole flash array (opt ionally without data flash) and separate write protection for all se ctors (only program flash). write protected se ctors can be made re- programmable (enabled with pass words), or they can be locked for ever (rom function). each sector can be a ssigned to up to three differen t users for write protection. the different users are orga nized hierarchically. program flash featu res and functions ?2 mbyte on-chip program flash in pmu0. ?2 mbyte on-chip program flash in pmu1. ? any use for instruction code or constant data. ? double flash module system approach: ? concurrent read acce ss of code and data. ? read while write (rww). ? concurrent program/era se in both modules. ?256 bit read interface (burst transfer operation). ? dynamic correction of single-b it errors during read access. ? transfer rate in burst mode: one 64-bit double-word per clock cycle. ? sector architecture: ?eight 16 kbyte, one 128 kbyte and seven 256 kbyte sectors. ? each sector separately erasable. ? each sector lockable for protection agai nst erase and program (write protection). ? one additional configuration sect or (not accessib le to the user). ? optional read protection for whole flash, with sophisticated read access supervision. combined with whole flash write protection ? thus supporting protection against trojan horse programs. ? sector specific write protection with support of re-programmability or locked forever. ? comfortable password checki ng for temporary disable of write or read protection. ? user controlled configuration blocks (ucb) in configuration sector for keywords and for sector-specific lock bits (one block for every us er; up to three users). ? pad supply voltage (v ddp ) also used for progra m and erase (no vpp pin). ? efficient 256 byte pa ge program operation. ? all flash operations contro lled by cpu per command se quences (unlock sequences) for protection agains t unintended operation. ? end-of-busy as well as error reporting with inte rrupt and bus error trap. ? write state machine for au tomatic program and erase, including verification of operation quality. ? support of margin check. ? delivery in erased state (read all zeros). ? global and sector status information. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 29 v1.1, 2009-04 ? overlay support wi th sram for calibr ation applications. ? configurable wait state selecti on for different cpu frequencies. ? endurance = 1000; minimum 1000 program/erase cycles per physical sector; reduced enduranc e of 100 per 16 kb sector. ? operating lifetime (incl. retent ion): 20 years with endurance=1000. ? for further operating conditi ons see data sheet section ?flash memory parameters?. data flash feat ures and functions note: only available in pmu0. ?64 kbyte on-chip flash, confi gured in two independent fl ash banks of equal size. ?64 bit read interface. ? erase/program one bank while data read access from the other bank. ? programming one bank while erasing the othe r bank using an automatic suspend/resume function. ? dynamic correction of single-b it errors during read access. ? sector architecture: ? two sectors of equal size. ? each sector separately erasable. ? 128 byte pages to be written in one step. ? operational control per co mmand sequences (u nlock sequences, sa me as those of program flash) for protection against unintend ed operation. ? end-of-busy as well as error reporting with inte rrupt and bus error trap. ? write state machine for au tomatic program and erase. ? margin check for detection of problematic flash bits. ? endurance = 30000 (can be device dep endent); i.e. 30000 prog ram/erase cycles per sector are allowed, with a retention of min. 5 years. ? dedicated dflash status information. ? other characteristics: same as program flash. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 30 v1.1, 2009-04 2.3.7 data access overlay the data overlay functionality provides the capability to re direct data accesses by the tricore to program memory (i nternal program flash or exte rnal memory) to the overlay sram in the pmu, or to th e emulation memory in emulat ion device ed, or to the external memory. this functionality makes it possible, for exam ple, to modify the application?s test and calibrat ion parameters (which are typically stor ed in the program memory) during run time of a pr ogram. note that read and write data accesses from/to program memory are redirected. attention: as the addr ess translation is impl emented in the dmi, it is only effective for data accesses by the tricore. instruction fetches by the tricore or accesses by any ot her master (including the debug interface) are not affected! note: the external memory ca n be used as overlay memory only in emulation devices ?ed? with an ebu. generally this feature is not supported in production devices ?pd?. however, this function is fu lly described here in this spec. summary of feat ures and functions ? 16 overlay ranges (?blocks?) configurable for program flash and exte rnal memory ? support of 8 kbyte embedded overlay sram (ovram) in pmu ? support of up to 512 kbyte overlay/calibration memory in emulation device (emem) ? support of up to 2 mb overlay memory in external memory (ebu space) ? support of online data ac quisition into range of up to 32 kb and of its overlay ? support of different overlay memory se lections for every en abled overlay block ? sizes of overlay blocks selectable from 16 byte to 2 kbyte for redirection to ovram ? sizes of overlay bloc ks selectable from 1 kbyte to 128 kbyte for redirection to emem or to external memory ? all configured overlay ranges can be en abled with only one re gister write access ? programmable flush (i nvalidate) control fo r data cache in dmi 2.4 development support overview about the TC1797 development environment: complete development support a variety of software and ha rdware development tools for the 32-bit microcontroller TC1797 are available from ex perienced international tool suppliers. t he development environment for the infineon 32-bit micr ocontroller in cludes the fo llowing tools: ? embedded development enviro nment for tricore products ? the TC1797 on-chip debu g support (ocds) provi des a jtag port for communication between external hardware and the system www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 31 v1.1, 2009-04 ? flexible peripheral interconnec t buses (fpi bus) for on-c hip interconnections and its fpi bus control unit (sbcu) ? the system timer (stm) with high-pre cision, long-range ti ming capabilities ? the TC1797 includes a power management system, a watchdog timer as well as reset logic www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 32 v1.1, 2009-04 2.5 on-chip peripheral units of the TC1797 the TC1797 microcontrol ler offers several ve rsatile on-chip periph eral units such as serial controllers, timer unit s, and analog-to-digital conver ters. several i/o lines on the TC1797 ports are reserved for these peripheral units to commu nicate with the external world. on-chip peripheral units ? two asynchronous/synchrono us serial channels (asc) with baud-rate generator, parity, framing and ov errun error detection ? two synchronous serial channels (ssc) with programmable data length and shift direction ? two micro second bus interfaces (msc) for serial communication ? one can module with four can nodes (mul tican) for high-effici ency data handling via fifo buffering and gateway data transfer ? two micro link serial bus interfaces (m li) for serial multip rocessor communication ? two general purpose timer ar rays (gpta) with a powerf ul set of digital signal filtering and timer fu nctionality to accomplish auto nomous and complex input/output management. one additional lo cal timer cell array (lcta). ? three analog-to-digital converter units (adc) with 8-bit, 10-bit, or 12-bit resolution. ? one fast analog-to-digi tal converter unit (fadc) ? one flexray tm module with 2 channels (e-ray). ? one external bus interface (ebu) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 33 v1.1, 2009-04 2.5.1 asynchronous/synchr onous serial interfaces the TC1797 includes two as ynchronous/synchronous se rial interfaces, asc0 and asc1. both asc modules have the same functionality. figure 5 shows a global view of the asynchro nous/synchronous seri al interface (asc). figure 5 general block diagram of the asc interface the asc provides serial communica tion between the TC1797 and other microcontrollers, microprocesso rs, or external peripherals. the asc supports full-dupl ex asynchronous communi cation and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock that is generated by the as c internally. in asynchronous mode, 8-bit or 9-bit data transfe r, parity generation , and the number of stop bits can be selected. parity, framing, and overrun erro r detection are provi ded to increase the reliability of data transfers. transmission and reception of data is double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is su pported by a loop-back option. a 13-bit baud rate generator provides the asc with a separat e serial clock sign al, which can be ac curately adjusted by a prescaler implemente d as fractional divider. mcb05762_mod clock control address decoder interrupt control f asc asc module (kernel) port control rxd txd rxd txd to dma eir tbir tir rir www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 34 v1.1, 2009-04 features ? full-duplex asynchro nous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity-bit generation/checking ? one or two stop bits ? baud rate from 5.625 mb it/s to 1.34 bit/s (@ 90 mhz module clock) ? multiprocessor mode for automati c address/data byte detection ? loop-back capability ? half-duplex 8-bit synchronous operating mode ? baud rate from 11.25 mb it/s to 915.5 bit/s (@ 90 mhz module clock) ? double-buffered tr ansmitter/receiver ? interrupt generation ? on a transmit buffe r empty condition ? on a transmit last bi t of a frame condition ? on a receive buffer full condition ? on an error condition (frame, parity, overrun error) ? implementation features ? connections to dma controller ? connections of receiver inpu t to gpta (ltc) for baud ra te detection and lin break signal measuring www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 35 v1.1, 2009-04 2.5.2 high-speed synchronous serial interfaces the TC1797 includes two high-speed synchronous seri al interfaces, ssc0 and ssc1. both ssc modules have the same functionality. figure 6 shows a global view of the synchronous serial interface (ssc). figure 6 general block diagram of the ssc interface the ssc supports full-duplex and half-duplex seri al synchronous communication up to 45 mbit/s (@ 90 mhz module clock, master mode). the serial clock signal can be generated by the ssc it self (master mode) or can be rece ived from an external master (slave mode). data width, shift direction, clock polarit y and phase are programmable. this allows communic ation with spi-compatible devices . transmission and reception of data are double-buffered. a shif t clock generator provides the ssc with a separate serial clock signal. one slave select input is available for sl ave mode operation. eight programmable slave select outputs (chip selects) are supported in master mode. mcb06058_mod clock control address decoder interrupt control f ssc ssc module (kernel) mrstb mtsr master rir tir eir slsi[7:1] slsi[7:1] slso[7:0] slso[7:0] mrst mtsr sclk mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port control f clc enable m/s select dma requests slsoando[7:0] slsoando[7:0] slsoandi[7:0] www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 36 v1.1, 2009-04 features ? master and slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of da ta bits: 2 to 16 bits ? programmable shift directio n: lsb or msb shift first ? programmable clock polarity : idle low or idle high state for the shift clock ? programmable clock/data phase: data shift wi th leading or trailing edge of the shift clock ? baud rate generation ? master mode: ? slave mode: ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, ph ase, baud rate, transmit error) ? flexible ssc pin configuration ? seven slave select inputs slsi[7:1] in slave mode ? eight programmable slave select outputs slso[7:0] in master mode ? automatic slso generation with programmable timing ? programmable active le vel and enable control ? combinable with slso output signals from other ssc modules www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 37 v1.1, 2009-04 2.5.3 micro second channel interface the TC1797 includes two micro second ch annel interfaces, ms c0 and msc1. both msc modules have the same functionality. each micro second channel (msc) interfac e provides serial communication links typically used to connect power switches or other peripheral devices. the serial communication link includes a fast sync hronous downstream channel and a slow asynchronous upst ream channel. figure 7 shows a global view of the interface signals of an msc interface. figure 7 general block diagra m of the msc interface the downstream and up stream channels of the msc module co mmunicate with the external world via nine i/o lines. eight ou tput lines are required for the serial communication of the downstream channel (clock, data, and enable signals). one out of eight input lines sdi[7:0] is us ed as serial data in put signal for the up stream channel. the source of the serial data to be transmit ted by the downstream channel can be msc register contents or data that is provided on the altinl /altinh input lines. these input lines are typically conn ected with other on-chip peripheral units (for example with a timer unit such as the gpta). an em ergency stop input si gnal makes it possible to set bits of the serial data stream to dedicated values in an emergency case. clock control, address decod ing, and interrupt service request contro l are managed outside the msc module kernel. service request outputs are ab le to trigger an interrupt or a dma request. 4 msc module (kernel) mcb06059 fcln clock control address decoder interrupt control f msc f clc downstream channel upstream channel fclp en0 en1 en2 en3 son sop sdi[7: 0] sr[3:0] emgstopmsc altinl[15:0] altinh[15:0] to dma 16 16 8 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 38 v1.1, 2009-04 features ? fast synchronous serial interface to connec t power switches in particular, or other peripheral devices via serial buses ? high-speed synchronous serial transmission on downstream channel ? serial output clock frequency: f fcl = f msc /2 ( f mscmax = 90 mhz) ? fractional clock divider for precise frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-contro lled, timer-controll ed, or free-running ? programmable upstream data fr ame length (16 or 12 bits) ? transmission with or without sel bit ? flexible chip select genera tion indicates status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 4, 8, 16, 32, 64, 128, or 256 ( f mscmax = 90 mhz) ? standard asynchronous serial frames ? parity error checker ? 8-to-1 input multiplexer for sdi lines ? built-in spike fi lter on sdi lines ? selectable pin types of dow nstream channel interface: four lvds differential output drivers or four digital gpio pins www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 39 v1.1, 2009-04 2.5.4 flexray? protocol controller (e-ray) the e-ray ip-module performs commun ication according to the flexray? 1) protocol specification v2.1. with ma ximum specified clock the bi trate can be programmed to values up to 10 mbit/s. additional bus driver (bd) ha rdware is required for connection to the physical layer. 2.5.4.1 e-ray kernel description figure 2.5.4.1 shows a global view of the e-ray interface. figure 8 general block diagram of the e-ray interface 1) infineon ? , infineon technologies ? , are trademarks of infineon technologies ag. flexray? is a trademark of flexray consortium. eray_overview.vsd address decoder interrupt control eray module (kernel) channel a channel b port control external request unit stop watch trigger select stpw mt external clock output f mt rxdb txdb txenb rxda txda txena clock control f clc_eray f sc l k f pll_eray f sys www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 40 v1.1, 2009-04 the e-ray module communicates with the external world via three i/o lines each channel. the rxdax and rxdb x lines are the receive data input signals, txda and txdb lines are the trans mit output signals, txena and txenb the transmit enable signals. clock control, address decodi ng, and service req uest control are ma naged outside the e-ray module kernel. 2.5.4.2 overview for communication on a flexra y? network, individual messag e buffers with up to 254 data byte are configurable. the message storage consists of a single-po rted message ram that holds up to 128 message buffers. all functions concer ning the handling of messages are implemented in the messag e handler. those functions are the acceptance filtering, the transfer of me ssages between the tw o flexray? channel protocol controllers and the message ram, maintaining the transm ission schedule as well as providing messag e status information. the register set of the e-ray ip-module can be accessed dire ctly by an external host via the module?s host interfac e. these registers are used to control/configure/monitor the flexray? channel protoc ol controllers, message ha ndler, global time unit, system universal control, frame and sy mbol processing, ne twork management, service request control, and to access the message ram via input / output buffer. the e-ray ip-module supports the following features: ? conformance with flexray? protocol specification v2.1 ? data rates of up to 10 mbit/s on each channel ? up to 128 message buffers configurable ?8 kbyte of message ram for storage of e.g. 128 mess age buffers wi th max. 48 byte data field or up to 30 message buffers with 254 byte data sections ? configuration of message buffers with different payload lengths possible ? one configurable receive fifo ? each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive fifo ? host access to mess age buffers via inpu t and output buffer. input buffer: holds message to be transferred to the message ram output buffer: holds message read from the message ram ? filtering for slot counter, cycle counter, and channel ? maskable module service requests ? network management supported ? four service request lines ? automatic delayed read access to output command request regi ster (obcr) if a data transfer from message ram to output shadow buffer (initiated by a previous write access to th e obcr) is ongoing. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 41 v1.1, 2009-04 ? automatic delayed read acce ss to input comma nd request register (ibcr) if a data transfer from input shadow bu ffer to message ram to (initiated by a previous write access to the ibcr) is ongoing. ? four input buffer for building up transmission frames in parallel. ? flag indicating which in put buffer is currently accessible by the host. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 42 v1.1, 2009-04 2.5.5 multican controller the multican module provides four independent can nodes, representing four serial communication interfaces. the number of available message obje cts is 128. figure 9 overview of the multican module the multican module contains four independently operat ing can nodes with full-can functionality that are able to exchange data and remote fr ames via a gateway function. transmission and reception of can frames is handle d in accordance to can specification v2.0 b (active) . each can node can receive a nd transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all four can nodes share a common set of me ssage objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and out going frames, me ssage objects can be combined to build gateways between the can node s or to set up a fifo buffer. the message objects are organi zed in double-chain ed linked lists, where each can node has its own list of mess age objects. a can node stores frames only into message objects that are allocated to the message object li st of the can node, and it transmits only messages be longing to this message object li st. a powerful, co mmand-driven list controller performs all mess age object li st operations. the bit timings for the ca n nodes are derived from the module ti mer clock ( f can ) and are programmable up to a data rate of 1 mbit/s. external bus tr ansceivers are connected to a can node via a pair of receive and transmit pins. multican module kernel mca06060_n4 can node 0 can control message object buffer 128 ob je cts can node 1 txdc0 rxdc0 txdc1 rxdc1 linked list control port control clock control address decoder interrupt control f can f clc can node 2 txdc2 rxdc2 can node 3 txdc3 rxdc3 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 43 v1.1, 2009-04 features ? compliant with iso 11898 ? can functionality according to can specificati on v2.0 b active ? dedicated control regist ers for each can node ? data transfer rates up to 1 mbit/s ? flexible and powerful message transfer control and error handling capabilities ? advanced can bus bit timing analysis and baud rate dete ction for each can node via a frame counter ? full-can functionality: a set of 128 message objects ca n be individually ? allocated (assigne d) to any can node ? configured as transmi t or receive object ? setup to handle frames with 11-bit or 29-bit identifier ? identified by a timest amp via a frame counter ? configured to remote monitoring mode ? advanced acceptance filtering ? each message object provides an individual acceptance mask to filter incoming frames. ? a message object can be c onfigured to accept standard or extended frames or to accept both standard and extended frames. ? message objects can be gr ouped into four priority classes for transmission and reception. ? the selection of the message to be tr ansmitted first can be based on frame identifier, ide bit and rtr bit according to can arbitration rules, or on its order in the list. ? advanced message ob ject functionality ? message objects can be comb ined to build fifo message buffers of arbitrary size, limited only by the total number of me ssage objects. ? message objects can be li nked to form a gateway th at automatically transfers frames between 2 different can buses. a single gateway ca n link any two can nodes. an arbitrary number of gateways can be defined. ? advanced data management ? the message objects are organ ized in double-chained lists. ? list reorganizations can be performed at any time, even during full oper ation of the can nodes. ? a powerful, command-driven list controller manages th e organization of the list structure and ensures co nsistency of the list. ? message fifos are based on the list st ructure and can easily be scaled in size during can operation. ? static allocation commands offe r compatibility with multic an applications that are not list-based. ? advanced interrupt handling www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 44 v1.1, 2009-04 ? up to 16 interrupt output lines are avai lable. interrupt reque sts can be routed individually to one of the 16 interrupt output lines. ? message post-processing notifications ca n be combined flexibly into a dedicated register field of 256 notification bits. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 45 v1.1, 2009-04 2.5.6 micro link serial bus interface this TC1797 contains two micro link serial bus in terfaces, mli0 and mli1. the micro link interface (mli) is a fast synchrono us serial interfac e to exchange data between microcontrollers or other devices, such as stand-alone peripheral components. figure 10 shows how two microcontrollers are typi cally connected together via their mli interfaces. figure 10 typical micro li nk interface connection features ? synchronous serial communication between an mli transmitter and an mli receiver ? different system clock spee ds supported in mli transmi tter and mli receiver due to full handshake prot ocol (4 lines be tween a transmitter and a receiver) ? fully transparent read/w rite access supported (= remote programming) ? complete address range of target device available ? specific frame protocol to tran sfer commands, addresses and data ? error detection by parity bit ? 32-bit, 16-bit, or 8-bit data transfers supported ? programmable baud rate: f mli /2 (max. f mli = f sys ) ? address range protec tion scheme to block unauthorized accesses ? multiple receiving devices supported mca06061 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 46 v1.1, 2009-04 figure 11 shows a general block di agram of the mli module. figure 11 general block diag ram of the mli modules the mli transmitter and mli receiver comm unicate with other ml i receivers and mli transmitters via a four-line serial connection each. several i/o lines of these connections are available outside the mli mo dule kernel as a four-line output or input vector with index numbering a, b, c and d. the mli module internal i/o control blocks define which signal of a vector is actual ly taken into account and also allow polarity inversions (to adapt to different physi cal intercon nection means) 4 mcb06062_mod port control tready[d:a] tvalid[d:a] rclk[d:a] mli transmitter mli receiver mli module tdata tclk rready[d:a] rvalid[d:a] rdata[d:a] fract. divider i/o control i/o control move engine sr[7:0] f ml i f sys brkout 4 4 4 4 4 tr[3:0] www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 47 v1.1, 2009-04 2.5.7 general purpose timer array (gpta) the TC1797 contains the general purpose timer array (gpta0), plus the additional local timer cell array (ltca2). figure 12 shows a global view of the gpta modules. the gpta provides a set of timer, compare, a nd capture functional ities that can be flexibly combined to form signal measurement and signal generatio n units. they are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to g enerate simple and complex signal waveforms required for other industrial applications. figure 12 general block diagram of the gpta modules in the TC1797 signal generation cells mcb05910_tc1767 gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 cl ock bus gpta0 clock generation cells clock conn . clock distribution cells f gpta ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltc 02 ltc 01 ltc 00 ltc 63 local timer cell array ltc 03 ltc 62 ltca2 i/o line sharing block i/o line sharing block interrupt sharing block interrupt sharing block www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 48 v1.1, 2009-04 2.5.7.1 functionality of gpta0 the general purpose timer array (gpta0) provides a set of hardware modules required for high-sp eed digital signal processing: ? filter and prescaler cells (f pc) support input noise filter ing and prescaler operation. ? phase discrimination logic units (pdl) deco de the direction information output by a rotation tracking system. ? duty cycle measurement cells (dcm ) provide pulse-width measurement capabilities. ? a digital phase lock ed loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. ? global timer units (gt) driv en by various clock sources are implemented to operate as a time base for the a ssociated global timer cells. ? global timer cells (gtc) can be programmed to capture the contents of a global timer on an external or inte rnal event. a gtc may also be us ed to control an external port pin depending on the result of an internal co mpare operation. gtcs can be logically concatenated to provide a common external po rt pin with a complex signal waveform. ? local timer cells (ltc) oper ating in timer, capture, or compare mode may also be logically tied together to drive a common exter nal port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mo de ? can be clocked or triggered by various extern al or internal events. ? on-chip trigger and gating signals (otgs) can be config ured to provide trigger or gating signals to integrated peripherals. input lines can be shared by an ltc and a gtc to trigger their programmed operation simultaneously. the following list summar izes the specific featur es of the gpta units. clock generation unit ? filter and prescaler cell (fpc) ? six independent units ? three basic o perating modes: prescaler, delayed de bounce filter, immedi ate debounce filter ? selectable input sources: port lines, gpta module clock, fpc output of preceding fpc cell ? selectable input clocks: gpta module clock, prescaled gpta modu le clock, dcm clock, compensated or uncompensated pll clock. ? f gpta /2 maximum input signal fr equency in filter modes ? phase discriminator logic (pdl) ? two independent units ? two operating modes (2- and 3- sensor signals) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 49 v1.1, 2009-04 ? f gpta /4 maximum input si gnal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode ? duty cycle measurement (dcm) ? four independent units ? 0 - 100% margin a nd time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ? one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution unit (cdu) ? one unit ? provides nine cl ock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation unit ? global timers (gt) ? two independent units ? two operating mode s (free-running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global timer cell (gtc) ? 32 units related to the global timers ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) ? 64 independent units ? three basic operating mo des (timer, capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt sharing unit ? 286 interrupt sources, generat ing up to 92 service requests www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 50 v1.1, 2009-04 on-chip trigger unit ? 16 on-chip trigger signals i/o sharing unit ? interconnecting inputs and outputs from inte rnal clocks, fpc, gtc, ltc, ports, and msc interface 2.5.7.2 functionality of ltca2 the local timer cell array (l tca2) provides a set of ha rdware modules required for high-speed digital signal processing: ? local timer cells (ltc) oper ating in timer, capture, or compare mode may also be logically tied together to drive a common exter nal port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mo de ? can be clocked or triggered by various extern al or internal events. the following list summar izes the specific feat ures of the ltca unit. the local timer arrays (ltca2) provides a set of hardware modul es required for high- speed digital signal processing: signal generation unit ? local timer cell (ltc) ? 32 independent units ? three basic operating mo des (timer, capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency i/o sharing unit ? interconnecting inputs and outputs from internal clocks, lt c, ports, and msc interface www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 51 v1.1, 2009-04 2.5.8 analog-to-digital converters the TC1797 includes th ree analog to digital conver ter modules (adc0, adc1, adc2) and one fast analog to digital converter (fadc). 2.5.8.1 adc block diagram the analog to digita l converter module (adc) allows th e conversion of analog input values into discrete digita l values based on the succe ssive approximation method. this module contains 3 independent kernels (adc0, adc1, adc2) that can operate autonomously or can be synchr onized to each other. an a dc kernel is a unit used to convert an analog input sig nal (done by an analog pa rt) and provid es means for triggering conversions, data handling and storage (done by a digital part). figure 13 adc module with three adc kernels features of the analog part of each adc kernel: adc_3_kernels ad converter analog part kernel 0 conversion control digital part kernel 0 ... analog inputs data (result) handling request control bus inter- face ad converter analog part kernel 1 conversion control digital part kernel 1 ... data (result) handling request control analog inputs ad converter analog part kernel 2 conversion control digital part kernel 2 ... data (result) handling request control analog inputs www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 52 v1.1, 2009-04 ? input voltage range from 0v to analog supply voltage ? analog supply voltage range from 3.3 v to 5 v (single supply) (5v nominal supply voltage, performance degradation accepted for lower voltages) ? input multiplexer width of 16 possible an alog input channels ( not all of them are necessarily available on pins) ? performance for 12 bit resolution (@f adci = 10 mhz): - conversion time about 2s, tue 1) of 4 lsb 12 @ operati ng voltage 5 v - conversion time about 2s, tue of 4 lsb 12 @ operating voltage 3.3 v ?v aref and 1 alternative refere nce input at channel 0 ? programmable sample ti me (in periods of f adci ) ? wide range of accepted a nalog clock frequencies f adci ? multiplexer test mode (chann el 7 input can be connected to ground via a resistor for test purposes during run time by specific control bit) ? power saving mechanisms features of the digital part of each adc kernel: ? independent result register s (16 independent registers) ? 5 conversion request sour ces (e.g. for external even ts, auto-scan, programmable sequence, etc.) ? synchronization of the adc kernel s for concurrent conversion starts ? control an external analog multiplexe r, respecting the a dditional set up time ? programmable sampling ti mes for different channels ? possibility to cancel ru nning conversions on dema nd with automatic restart ? flexible interrupt generation (possibility of dma support) ? limit checking to r educe interrupt load ? programmable data redu ction filter by adding conversion results ? support of conversion data fifo ? support of suspend and power down modes ? individually programmable re ference selection for each channel (with exception of dedicated channels alwa ys referring to v aref ) 1) this value reflects the adc module capability in an adapted electrical environment, e.g. characterized by ?clean? routing of analog and digital signals and separation of analog and digital pcb areas, low noise on analog power supply (< 30mv), low switching activity of digital pins near to the adc, etc. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 53 v1.1, 2009-04 2.5.8.2 fadc short description general features ? extreme fast conversion, 21 cycles of f fadc clock (262.5 ns @ f fadc = 80 mhz) ? 10-bit a/d conversion (hi gher resolution can be ac hieved by averaging of consecutive conversions in di gital data reduction filter) ? successive approximation conversion method ? two differential input channels with im pedance control availabl e on dedicated pins ? two differential input channels with im pedance control overlaid with adc1 inputs ? each differential input channel can also be used as single-ended input ? offset calibration su pport for each channel ? programmable gain of 1, 2, 4, or 8 for each channel ? free-running (channel timers) or triggered conversion modes ? trigger and gating cont rol for external signals ? built-in channel timers for internal triggering ? channel timer request periods indep endently selectable for each channel ? selectable, programmable digita l anti-aliasing and data reduction filter block with four independent filter units figure 14 block diagram of the fadc module with 4 input channels srx mcb06065_m4 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control ts[h:a] gs[h:a] clock control f fadc f clc a/d converter stage data reduction unit fain0p fain0n fain1p fain1n input structure channel trigger control channel timers srx dma a/d control v ddif input channel 0 input channel 1 fain2p fain2n fain3p fain3n input channel 2 input channel 3 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 54 v1.1, 2009-04 as shown in figure 14 , the main fadc func tional blocks are: ? an input structure containing the diffe rential inputs and impedance control. ? an a/d converter stage responsible for the analog-to-digital conv ersion including an input multiplexer to select between the channel amplifiers ? a data reduction unit containing prog rammable anti-aliasing and data reduction filters ? a channel trigger co ntrol block determining the trigge r and gating conditions for the fadc channels ? a channel timer for each channel to independently trigger the conversions ? an a/d control block responsible fo r the overall fadc functionality fadc power supply and references the fadc module is su pplied by the following power supp ly and referenc e voltage lines: ? v ddmf / v ssmf : fadc analog channel ampl ifier power supply (3.3 v) ? v ddif / v ssmf : fadc analog input stage power supply (3.3 - 5 v), the v ddif supply does not appear as supply pin, because it is internally connected to the v ddm supply of the adc that is sharing the fadc input pins. ? v ddaf / v ssaf : fadc analog part po wer supply (1.5 v), to be fed in externally ? v faref / v fagnd : fadc reference voltage (3.3 v max.) and fadc reference ground input structure the input structure of the fadc in the TC1797 contains: ? a differential analog input stage for each input channel to select the input impedance (differential or single-en ded measurement) and to de couple the fadc input signal from the pins. ? input channels 2 and 3 are overlaid with adc1 input signals (an28, an29, an30, an31), whereas input channels 0 and 1 are available on dedicated input pins (an32, an33, an34, an35). ? a channel amplifier for each input channel with a settling time (about 5s) when changing the characteristics of an input stage (changing between unused, differential, singl e-ended n, or si ngle-ended p mode). www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 55 v1.1, 2009-04 figure 15 fadc input st ructure in TC1797 mca06432_m4n fain0n fain0p analog input stages rp rn channel amplifier stages gain a/d a/d control conversion control converter stage chnr v ddaf v ssaf fain2n fain2p rp rn fain1n fain1p rp rn v ddif fain3n fain3p rp rn v ssmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf v ssmf v ddmf www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 56 v1.1, 2009-04 2.5.9 external bus interface the external bus unit (ebu) of the TC1797 contro ls the accesses fr om peripheral units to external memories. features: ? 64-bit internal lmb interface ? 32-bit demultiplexed / 16-bit multiplex ed external bus inte rface (3.3v, 2.5v) ? support for intel-style and moto rola-style interface signals ? support for burst flash memory devices ? flexibly programmabl e access parameters ? programmable chip select lines ? little-endian support ? examples for memories th at has to be supported ? burst flash: ? spansion: s29cd016, s29cd032 ? spansion: s29cl0 32j1rfam010 @3,3v ? st: m58bw016, m58bw032 ? st: m58bw032gb b45za3t @3,3v ? flash (for 16 bit muxed mode): ? http://www.spansion.com/pr oducts/am29lv160b.html ? sram (for 16 bit muxed mode): ? http://www.idt.com/pro ducts/files/10372/71 v016saautomotive.pdf ? http://213.174.55.51/zmd.b iz/pdf/ ul62h1616a.pdf ? idt 71v416ys15bei ? scalable external bus frequency ? derived from lmb frequency ( f cpu ) divided by 1, 2, 3, or 4 ? maximum 75 mhz 1) ? data buffering supported ? code prefetch buffer ? read/write buffer 2.6 on-chip debug support (ocds) the TC1797 contains resources for different kinds of ?debu gging?, covering needs from software development to real -time-tuning. these resource s are either embedded in specific modules (e.g. breakpoint logic of th e tricore) or part of a central peripheral (known as c erberus ). 1) maximum frequency of today available automotive burst flash devices. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 57 v1.1, 2009-04 2.6.1 on-chip debug support the classic software debug approach (start/s top, single-stepping) is supported by several features labe lled ?ocds level 1?: ? run/stop and single-step executio n independently for tricore and pcp. ? means to request all kinds of reset without usage of sideband pins. ? halt-after-reset for re peatable debug sessions. ? different boot modes to use application software not yet programmed to the flash. ? a total of four hardware breakpoints for the tricore based on inst ruction address, data address or co mbination of both. ? unlimited number of software breakpoints (debug instruction) for tricore and pcp. ? debug event genera ted by access to a specific address via the system bus. ? tool access to all sfrs and internal memories independe nt of the cores. ? two central break switches to collect deb ug events from all mo dules (tricore, pcp, dma, bcu, break input pins) and distribute them selectively to breakable modules (tricore, pcp, break output pins). ? central suspend switch to suspend parts of the system (tricore, pcp, peripherals) instead if breaking them as reaction to a debug event. ? dedicated interrupt resource s to handle debug events in side tricore (breakpoint trap, software interrupt) and cerberus (can trigger pcp), e.g. for implementing monitor programs. ? access to all ocds level 1 resources also for tricor e and pcp themselves for debug tools integrated in to the application code. ? triggered transfer of data in response to a debug event; if target is programmed to be a device interface simple variable tracin g can be done. ? in depth performance analysi s and profiling support give n by the emulation device through mcds event counters driven by a variety of trig ger signals (e.g. cache hit, wait state, interrupt accepted). 2.6.2 real time trace for detailed tracing of the sy stem?s behavior a pin-compatib le emulation device will be available. 1) 2.6.3 calibration support two main use cases are catered for by resources in additio n the ocds level 1 infrastructure: overlay of non-volatile on-chip memory and non-intrusive signaling: ? 8 kb sram for overlay. ? can be split into up to 16 blocks whic h can overlay independen t regions of on-chip data flash. 1) the ocds l2 interface of audong is not available. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 58 v1.1, 2009-04 ? changing the configur ation is triggered by a sing le sfr access to maintain consistency. ? overlay configuration swit ch does not require the tricore to be stopped or suspended. ? invalidation of the data cache (maint aining write-back data) can be done concurrently with the same sfr. ?256 kb additional overlay ra m on emulation device. ? the 256 kb trace memory of the emulation de vice can optionall y be used for overlay also. ? a dedicated trigger sfr with 32 independent status bits is provided to centrally post requests from application code to the host computer. ? the host is notifi ed automatically when the trigger sfr is updated by the tricore or pcp. no polling via a system bus is required. 2.6.4 tool interfaces three options exist for the communicatio n channel between to ols (e.g. debugger, calibration to ol) and TC1797: ? two wire dap (device access port) pr otocol for long co nnections or noisy environments. ? four (or five) wire jtag (ieee 1149.1) for standardized m anufacturing tests. ? can (plus software linked into the applic ation code) for lo w bandwidth deeply embedded purposes. ? dap and jtag are cl ocked by the tool. ? bit clock up to 40 mhz for jtag, up to 80 mhz for dap. ? hot attach (i.e. physical di sconnect/reconnect of the host connecti on without reset of the TC1797) for all interfaces. ? infineon standard das (d evice access server) impl ementation for seamless, transparent tool ac cess over any supported interface. ? lock mechanism to prevent unauthorized tool access to critical application code. 2.6.5 self-test support some manufacturing tests can be invoked by the application (e.g. after power-on) if needed: ? hardware-accelerated checksum ca lculation (e.g. for flash content). ? ram tests optimized for th e implemented architecture. 2.6.6 far support to efficiently locate an d identify faults after integration of a TC1797 into a system special functions are available: ? boundary scan (ieee 114 9.1) via jtag and dap. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 introduction data sheet 59 v1.1, 2009-04 ? sscm (single scan chain mode 1) ) for structural scan test ing of the chip itself. 1) this function requires access to some device pins (e.g. testmode ) in addition to those needed for ocds. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 60 v1.1, 2009-04 3 pinning 3.1 TC1797 pin definition and functions: p/pg-bga-416-10 figure 16 is showing the TC1797 logic sy mbol for the package variant: p/pg-bga-416-10. figure 16 TC1797 logic symbol for the package variant p/pg-bga-416-10 TC1797 _logsym_416 alternate functions: xtal2 xtal1 oscillator v ss v dd 13 79 digital circuitry power supply v ddp 11 v ddfl3 v ddsbram TC1797 fadc analog power supply v arefx v agndx v ddm adc0 /adc1 analog power supply an[43:0] adc analog inputs port 0 port 1 port 2 port 4 port 5 port 3 gpta gpta / ssc0 / ssc1 port 6 port 7 port 8 port 9 port 10 gpta / mli0 / eru / ssc1 asc0 / asc1 / msc0 / msc1 / lvds / mli0 eru / adc-mux mli1 / gpta 3 v ddebu 9 v ssosc / v ss v ddosc3 3 n.c. 9 v ddosc 3 6 15 8 8 12 16 16 16 16 16 16 e-ray / gpta / hwcfg port 11 16 ebu port 12 8 ebu port 13 16 gpta / ebu port 14 16 gpta / ebu port 15 ebu 16 port 16 4 ebu v ssm trst tck / dap0 tdi / brkin/ brkout tdo /brkout/ dap2 / brkin tms / dap1 ocds / jtag control testmode esr0 porst general control esr1 v ddpf3c3 v ddpf v ssmf v ssaf v fagnd v faref v ddmf v ddaf asc0 / asc1 / ssc1 / can / e-ray msc0 / msc1 / gpta www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 61 v1.1, 2009-04 3.1.1 TC1797 p/pg-bga-416-10 package variant pin configuration figure 17 shows the TC1797 pin configuratio n for the p/pg-bga-416-10 package variant. figure 17 TC1797 pinning for p/pg-bga-416-10 package mca05584_97.vsd v agnd1 v aref1 v dd v ddm v ssm po rst v ss v agnd0 v aref0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p2.9 p2.6 p2.13 p2.15 p2.14 p2.12 p2.11 p2.10 p2.7 p2.5 p2.8 p2.2 p2.4 p2.3 p0.15 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 an22 an21 an19 an16 an23 an20 an17 an13 an18 an14 an10 an15 an11 an5 an2 an12 an9 an3 an7 an8 an4 an32 an38 an6 an1 an34 an40 an0 an33 an36 an41 an37 an39 an43 an42 an35 an28 an29 an26 an27 an24 an25 an30 an31 v fagnd v faref v dd v ss v ddp p6.9 p6.8 p6.5 p1.11 p1.5 p1.12 p1.4 v dd v ss p7.2 v dd v ss v dd v ddp v ddp v ss v dd v ss v ddp v ss v dd v ddp v ss v dd v ddp v ss v dd v ddp v ddebu v ddebu v ddebu v ddebu v ddebu v ss v dd v dd v ddebu v ddebu v dd v ss n.c. v ss v ss tdo tck tdi trst tms xtal 2 xtal 1 v ss osc v dd osc v dd osc3 p0.14 p0.9 p0.5 p0.6 p0.2 p0.4 p0.8 p0.1 p0.3 p0.7 p0.12 p0.10 p0.13 p0.11 p0.0 p3.15 p3.7 p3.14 p3.6 p3.10 p3.8 p3.9 p3.12 p3.4 p3.13 p3.11 p3.2 p3.5 p3.3 p3.1 p3.0 p5.1 p5.0 p5.2 p5.3 p5.7 p5.6 p5.5 p5.4 p5.12 p5.13 p5.9 p5.15 p5.14 p5.10 v ddfl3 v ddfl3 p5.11 p5.8 p9.4 p9.5 p9.6 p9.1 p9.0 p9.7 p9.8 p9.2 p9.3 p9.12 p9.11 p9.10 p9.9 n.c. p6.12 p6.11 p6.6 p6.14 p6.10 p6.4 p6.15 p6.13 p6.7 p8.1 p8.0 p8.4 p8.3 p8.7 p8.5 p8.2 p8.6 p1.15 p1.14 p1.13 p1.10 p1.9 p1.8 p1.3 p1.7 p1.6 p1.2 p1.1 p1.0 v dd sbram p7.6 p7.1 p7.0 p7.4 p7.3 p7.7 p7.5 v ssmf v ddmf v aref2 v ddaf p4.4 p4.8 p4.3 p4.12 p4.15 p4.11 p4.13 p4.2 p4.10 p4.7 p4.5 p4.14 p4.6 p4.9 p4.0 p4.1 p10.4 p10.3 v ddp v ddp v ddp v ddp v ss v ss v ddebu v dd v ddebu n.c. n.c. n.c. n.c. v ss v ss v ss v ss v ss v ss v ss v ss n.c. n.c. n.c. v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss test mode v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss esr0 p9.13 p9.14 v ddpf v ddpf3 p10.5 p10.2 p10.0 p10.1 p15.5 p15.4 p16.0 p16.1 p15.7 p15.6 p15.3 p16.3 p15. 12 p15. 11 p15.2 p15.8 p15.1 p15.9 p15.0 p16.2 p15. 10 p15. 13 p15. 14 p15. 15 p11.3 p11.7 p12.6 p12.7 p11.0 p11.4 p11.1 p11.2 p11. 11 p11.6 p11.5 p11. 10 p11.8 p11.9 p11. 13 p11. 14 p11. 15 p11. 12 p12.1 p12.2 p12.0 p12.3 p12.5 p12.4 p13.1 p13.3 p13.0 p13.6 p13.9 p13.5 p13.2 p13. 13 p13.8 p13.4 p13. 12 p13.7 p14.0 p13. 14 p13. 10 p14.2 p14.3 p14.6 p14.1 p13. 11 p14.5 p14.4 p14. 12 p14.9 p14. 15 p14. 14 p14. 11 p14. 13 p14. 10 p14.8 p14.7 p13. 15 esr1 v ddfl3 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 62 v1.1, 2009-04 table 4 pin definitions and funct ions (bga-416 package) pin symbol ctrl. type function port 0 a9 p0.0 i/o0 a1/ pu port 0 general purpose i/o line 0 hwcfg0 i hardware configuration input 0 out56 o1 out56 line of gpta0 out56 o2 out56 line of gpta1 out80 o3 out80 line of ltca2 a8 p0.1 i/o0 a1/ pu port 0 general purpose i/o line 1 hwcfg1 i hardware configuration input 1 out57 o1 out57 line of gpta0 out57 o2 out57 line of gpta1 out81 o3 out81 line of ltca2 a7 p0.2 i/o0 a1/ pu port 0 general purpose i/o line 2 hwcfg2 i hardware configuration input 2 out58 o1 out58 line of gpta0 out58 o2 out58 line of gpta1 out82 o3 out82 line of ltca2 b8 p0.3 i/o0 a1/ pu port 0 general purpose i/o line 3 hwcfg3 i hardware configuration input 3 out59 o1 out59 line of gpta0 out59 o2 out59 line of gpta1 out83 o3 out83 line of ltca2 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 63 v1.1, 2009-04 b7 p0.4 i/o0 a1/ pu port 0 general purpose i/o line 4 hwcfg4 i hardware configuration input 4 out60 o1 out60 line of gpta0 out60 o2 out60 line of gpta1 out84 o3 out84 line of ltca2 a6 p0.5 i/o0 a1/ pu port 0 general purpose i/o line 5 hwcfg5 i hardware configuration input 5 out61 o1 out61 line of gpta0 out61 o2 out61 line of gpta1 out85 o3 out85 line of ltca2 b6 p0.6 i/o0 a1/ pu port 0 general purpose i/o line 6 hwcfg6 i hardware configuration input 6 out62 o1 out62 line of gpta0 out62 o2 out62 line of gpta1 out86 o3 out86 line of ltca2 c8 p0.7 i/o0 a1/ pu port 0 general purpose i/o line 7 hwcfg7 i hardware configuration input 7 out63 o1 out63 line of gpta0 out63 o2 out63 line of gpta1 out87 o3 out87 line of ltca2 c7 p0.8 i/o0 a1/ pu port 0 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 64 v1.1, 2009-04 b5 p0.9 i/o0 a1/ pu port 0 general purpose i/o line 9 rxda0 i e-ray channel a receive data input 0 reserved o1 - reserved o2 - reserved o3 - c6 p0.10 i/o0 a2/ pu port 0 general purpose i/o line 10 txena o1 e-ray channel a transmit data output enable reserved o2 - reserved o3 - d6 p0.11 i/o0 a2/ pu port 0 general purpose i/o line 11 txenb o1 e-ray channel b transmit data output enable reserved o2 - reserved o3 - c5 p0.12 i/o0 a2/ pu port 0 general purpose i/o line 12 txdb o1 e-ray channel b transmit data output reserved o2 - reserved o3 - d5 p0.13 i/o0 a1/ pu port 0 general purpose i/o line 13 rxdb0 i e-ray channel b receive data input 0 reserved o1 - reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 65 v1.1, 2009-04 a5 p0.14 i/o0 a2/ pu port 0 general purpose i/o line 14 txda o1 e-ray channel a transmit data output reserved o2 - reserved o3 - d4 p0.15 i/o0 a1/ pu port 0 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - port 1 p3 p1.0 i/o0 a2/ pu port 1 general purpose i/o line 0 req0 i external trigger input 0 extclk1 o1 external clock output 1 reserved o2 - reserved o3 - p2 p1.1 i/o0 a1/ pu port 1 general purpose i/o line 1 req1 i external trigger input 1 reserved o1 - reserved o2 - reserved o3 - p1 p1.2 i/o0 a1/ pu port 1 general purpose i/o line 2 req2 i external trigger input 2 reserved o1 - reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 66 v1.1, 2009-04 n1 p1.3 i/o0 a1/ pu port 1 general purpose i/o line 3 req3 i external trigger input 3 tready0b i mli0 transmit cha nnel ready input b reserved o1 - reserved o2 - reserved o3 - n4 p1.4 i/o0 a2/ pu port 1 general purpose i/o line 4 tclk0 o1 mli0 transmit channel clock output reserved o2 - reserved o3 - m4 p1.5 i/o0 a1/ pu port 1 general purpose i/o line 35 tready0a i mli0 transmit cha nnel ready input a reserved o1 - reserved o2 - reserved o3 - n3 p1.6 i/o0 a2/ pu port 1 general purpose i/o line 6 tvalid0a o1 mli0 transmit cha nnel valid output a slso10 o2 slave select output line 10 reserved o3 - n2 p1.7 i/o0 a2/ pu port 1 general purpose i/o line 7 tdata0 o1 mli0 transmit ch annel data output reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 67 v1.1, 2009-04 m3 p1.8 i/o0 a1/ pu port 1 general purpose i/o line 8 rclk0a i mli0 receive cha nnel clock input a out64 o1 out64 line of gpta0 out64 o2 out64 line of gpta1 out88 o3 out88 line of ltca2 m2 p1.9 i/o0 a2/ pu port 1 general purpose i/o line 9 rready0a o1 mli0 receive channel ready output a slso11 o2 slave select output line 11 out65 o3 out65 line of gpta0 m1 p1.10 i/o0 a1/ pu port 1 general purpose i/o line 10 rvalid0a i mli0 receive cha nnel valid input a out66 o1 out66 line of gpta0 out66 o2 out66 line of gpta1 out90 o3 out90 line of ltca2 l4 p1.11 i/o0 a1/ pu port 1 general purpose i/o line 11 rdata0a i mli0 receive cha nnel data input a out67 o1 out67 line of gpta0 out67 o2 out67 line of gpta1 out91 o3 out91 line of ltca2 p4 p1.12 i/o0 a2/ pu port 1 general purpose i/o line 12 extclk0 o1 external clock output 0 out68 o2 out68 line of gpta0 out68 o3 out68 line of gpta1 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 68 v1.1, 2009-04 l3 p1.13 i/o0 a1/ pu port 1 general purpose i/o line 13 rclk0b i mli0 receive cha nnel clock input b out69 o1 out69 line of gpta0 out69 o2 out69 line of gpta1 out93 o3 out93 line of ltca2 l2 p1.14 i/o0 a1/ pu port 1 general purpose i/o line 14 rvalid0b i mli0 receive cha nnel valid input b out70 o1 out70 line of gpta0 out70 o2 out70 line of gpta1 out94 o3 out94 line of ltca2 l1 p1.15 i/o0 a1/ pu port 1 general purpose i/o line 15 rdata0b i mli0 receive cha nnel data input b out70 o1 out71 line of gpta0 out70 o2 out71 line of gpta1 out95 o3 out95 line of ltca2 port 2 d3 p2.2 i/o0 a2/ pu port 2 general purpose i/o line 2 slso02 o1 slave select output line 2 slso12 o2 slave select output line 12 slso02 and slso12 o3 slave select output line 2 and slave select output line 12 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 69 v1.1, 2009-04 d2 p2.3 i/o0 a2/ pu port 2 general purpose i/o line 3 slso03 o1 slave select output line 3 slso13 o2 slave select output line 13 slso03 and slso13 o3 slave select output line 3 and slave select output line 13 d1 p2.4 i/o0 a2/ pu port 2 general purpose i/o line 4 slso04 o1 slave select output line 4 slso14 o2 slave select output line 14 slso04 and slso14 o3 slave select output line 4 and slave select output line 14 c1 p2.5 i/o0 a2/ pu port 2 general purpose i/o line 5 slso05 o1 slave select output line 5 slso15 o2 slave select output line 15 slso05 and slso15 o3 slave select output line 5 and slave select output line 15 b1 p2.6 i/o0 a2/ pu port 2 general purpose i/o line 6 slso06 o1 slave select output line 6 slso16 o2 slave select output line 16 slso06 and slso16 o3 slave select output line 6 and slave select output line 16 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 70 v1.1, 2009-04 b2 p2.7 i/o0 a2/ pu port 2 general purpose i/o line 7 slso07 o1 slave select output line 7 slso17 o2 slave select output line 17 slso07 and slso17 o3 slave select output li ne 7and slave select output line 17 c2 p2.8 i/o0 a1/ pu port 2 general purpose i/o line 8 in0 i in0 line of gpta0 in0 i in0 line of gpta1 in0 i in0 line of ltca2 out0 o1 out0 line of gpta0 out0 o2 out0 line of gpta1 out0 o3 out0 line of ltca2 a2 p2.9 i/o0 a1/ pu port 2 general purpose i/o line 9 in1 i in1 line of gpta0 in1 i in1 line of gpta1 in1 i in1 line of ltca2 out1 o1 out1 line of gpta0 out1 o2 out1 line of gpta1 out1 o3 out1 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 71 v1.1, 2009-04 b3 p2.10 i/o0 a1/ pu port 2 general purpose i/o line 10 in2 i in2 line of gpta0 in2 i in2 line of gpta1 in2 i in2 line of ltca2 out2 o1 out2 line of gpta0 out2 o2 out2 line of gpta1 out2 o3 out2 line of ltca2 c3 p2.11 i/o0 a1/ pu port 2 general purpose i/o line 11 in3 i in3 line of gpta0 in3 i in3 line of gpta1 in3 i in3 line of ltca2 out3 o1 out3 line of gpta0 out3 o2 out3 line of gpta1 out3 o3 out3 line of ltca2 c4 p2.12 i/o0 a1/ pu port 2 general purpose i/o line 12 in4 i in4 line of gpta0 in4 i in4 line of gpta1 in4 i in4 line of ltca2 out4 o1 out4 line of gpta0 out4 o2 out4 line of gpta1 out4 o3 out4 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 72 v1.1, 2009-04 a3 p2.13 i/o0 a1/ pu port 2 general purpose i/o line 13 in5 i in5 line of gpta0 in5 i in5 line of gpta1 in5 i in5 line of ltca2 out5 o1 out5 line of gpta0 out5 o2 out5 line of gpta1 out5 o3 out5 line of ltca2 b4 p2.14 i/o0 a1/ pu port 2 general purpose i/o line 14 in6 i in6 line of gpta0 in6 i in6 line of gpta1 in6 i in6 line of ltca2 out6 o1 out6 line of gpta0 out6 o2 out6 line of gpta1 out6 o3 out6 line of ltca2 a4 p2.15 i/o0 a1/ pu port 2 general purpose i/o line 15 in7 i in7 line of gpta0 in7 i in7 line of gpta1 in7 i in7 line of ltca2 out7 o1 out7 line of gpta0 out7 o2 out7 line of gpta1 out7 o3 out7 line of ltca2 port 3 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 73 v1.1, 2009-04 b12 p3.0 i/o0 a1/ pu port 3 general purpose i/o line 0 in8 i in8 line of gpta0 in8 i in8 line of gpta1 in8 i in8 line of ltca2 out8 o1 out8 line of gpta0 out8 o2 out8 line of gpta1 out8 o3 out8 line of ltca2 a12 p3.1 i/o0 a1/ pu port 3 general purpose i/o line 1 in9 i in9 line of gpta0 in9 i in9 line of gpta1 in9 i in9 line of ltca2 out9 o1 out9 line of gpta0 out9 o2 out9 line of gpta1 out9 o3 out9 line of ltca2 c13 p3.2 i/o0 a1/ pu port 3 general purpose i/o line 2 in10 i in10 line of gpta0 in10 i in10 line of gpta1 in10 i in10 line of ltca2 out10 o1 out10 line of gpta0 out10 o2 out10 line of gpta1 out10 o3 out10 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 74 v1.1, 2009-04 b11 p3.3 i/o0 a1/ pu port 3 general purpose i/o line 3 in11 i in11 line of gpta0 in11 i in11 line of gpta1 in11 i in11 line of ltca2 out11 o1 out11 line of gpta0 out11 o2 out11 line of gpta1 out11 o3 out11 line of ltca2 c12 p3.4 i/o0 a1/ pu port 3 general purpose i/o line 4 in12 i in12 line of gpta0 in12 i in12 line of gpta1 in12 i in12 line of ltca2 out12 o1 out12 line of gpta0 out12 o2 out12 line of gpta1 out12 o3 out12 line of ltca2 a11 p3.5 i/o0 a1/ pu port 3 general purpose i/o line 5 in13 i in13 line of gpta0 in13 i in13 line of gpta1 in13 i in13 line of ltca2 out13 o1 out13 line of gpta0 out13 o2 out13 line of gpta1 out13 o3 out13 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 75 v1.1, 2009-04 b10 p3.6 i/o0 a1/ pu port 3 general purpose i/o line 6 in14 i in14 line of gpta0 in14 i in14 line of gpta1 in14 i in14 line of ltca2 out14 o1 out14 line of gpta0 out14 o2 out14 line of gpta1 out14 o3 out14 line of ltca2 c9 p3.7 i/o0 a1/ pu port 3 general purpose i/o line 7 in15 i in15 line of gpta0 in15 i in15 line of gpta1 in15 i in15 line of ltca2 out15 o1 out15 line of gpta0 out15 o2 out15 line of gpta1 out15 o3 out15 line of ltca2 d10 p3.8 i/o0 a1/ pu port 3 general purpose i/o line 8 in16 i in16 line of gpta0 in16 i in16 line of gpta1 in16 i in16 line of ltca2 out16 o1 out16 line of gpta0 out16 o2 out16 line of gpta1 out16 o3 out16 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 76 v1.1, 2009-04 c11 p3.9 i/o0 a1/ pu port 3 general purpose i/o line 9 in17 i in17 line of gpta0 in17 i in17 line of gpta1 in17 i in17 line of ltca2 out17 o1 out17 line of gpta0 out17 o2 out17 line of gpta1 out17 o3 out17 line of ltca2 c10 p3.10 i/o0 a1/ pu port 3 general purpose i/o line 10 in18 i in18 line of gpta0 in18 i in18 line of gpta1 in18 i in18 line of ltca2 out18 o1 out18 line of gpta0 out18 o2 out18 line of gpta1 out18 o3 out18 line of ltca2 d13 p3.11 i/o0 a1/ pu port 3 general purpose i/o line 11 in19 i in19 line of gpta0 in19 i in19 line of gpta1 in19 i in19 line of ltca2 out19 o1 out19 line of gpta0 out19 o2 out19 line of gpta1 out19 o3 out19 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 77 v1.1, 2009-04 d11 p3.12 i/o0 a1/ pu port 3 general purpose i/o line 12 in20 i in20 line of gpta0 in20 i in20 line of gpta1 in20 i in20 line of ltca2 out20 o1 out20 line of gpta0 out20 o2 out20 line of gpta1 out20 o3 out20 line of ltca2 d12 p3.13 i/o0 a1/ pu port 3 general purpose i/o line 13 in21 i in21 line of gpta0 in21 i in21 line of gpta1 in21 i in21 line of ltca2 out21 o1 out21 line of gpta0 out21 o2 out21 line of gpta1 out21 o3 out21 line of ltca2 a10 p3.14 i/o0 a1/ pu port 3 general purpose i/o line 14 in22 i in22 line of gpta0 in22 i in22 line of gpta1 in22 i in22 line of ltca2 out22 o1 out22 line of gpta0 out22 o2 out22 line of gpta1 out22 o3 out22 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 78 v1.1, 2009-04 b9 p3.15 i/o0 a1/ pu port 3 general purpose i/o line 15 in23 i in23 line of gpta0 in23 i in23 line of gpta1 in23 i in23 line of ltca2 out23 o1 out23 line of gpta0 out23 o2 out23 line of gpta1 out23 o3 out23 line of ltca2 port 4 ad10 p4.0 i/o0 a2/ pu port 4 general purpose i/o line 0 in24 i in24 line of gpta0 in24 i in24 line of gpta1 in24 i in24 line of ltca2 out24 o1 out24 line of gpta0 out24 o2 out24 line of gpta1 out24 o3 out24 line of ltca2 ae10 p4.1 i/o0 a2/ pu port 4 general purpose i/o line 1 in25 i in25 line of gpta0 in25 i in25 line of gpta1 in25 i in25 line of ltca2 out25 o1 out25 line of gpta0 out25 o2 out25 line of gpta1 out25 o3 out25 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 79 v1.1, 2009-04 ad11 p4.2 i/o0 a2/ pu port 4 general purpose i/o line 2 in26 i in26 line of gpta0 in26 i in26 line of gpta1 in26 i in26 line of ltca2 out26 o1 out26 line of gpta0 out26 o2 out26 line of gpta1 out26 o3 out26 line of ltca2 ae11 p4.3 i/o0 a2/ pu port 4 general purpose i/o line 3 in27 i in27 line of gpta0 in27 i in27 line of gpta1 in27 i in27 line of ltca2 out27 o1 out27 line of gpta0 out27 o2 out27 line of gpta1 out27 o3 out27 line of ltca2 ac12 p4.4 i/o0 a2/ pu port 4 general purpose i/o line 4 in28 i in28 line of gpta0 in28 i in28 line of gpta1 in28 i in28 line of ltca2 out28 o1 out28 line of gpta0 out28 o2 out28 line of gpta1 out28 o3 out28 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 80 v1.1, 2009-04 ad12 p4.5 i/o0 a2/ pu port 4 general purpose i/o line 5 in29 i in29 line of gpta0 in29 i in29 line of gpta1 in29 i in29 line of ltca2 out29 o1 out29 line of gpta0 out29 o2 out29 line of gpta1 out29 o3 out29 line of ltca2 af10 p4.6 i/o0 a2/ pu port 4 general purpose i/o line 6 in30 i in30 line of gpta0 in30 i in30 line of gpta1 in30 i in30 line of ltca2 out30 o1 out30 line of gpta0 out30 o2 out30 line of gpta1 out30 o3 out30 line of ltca2 ae12 p4.7 i/o0 a2/ pu port 4 general purpose i/o line 7 in31 i in31 line of gpta0 in31 i in31 line of gpta1 in31 i in31line of ltca2 out31 o1 out31 line of gpta0 out31 o2 out31 line of gpta1 out31 o3 out31 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 81 v1.1, 2009-04 ac13 p4.8 i/o0 a1/ pu port 4 general purpose i/o line 8 in32 i in32 line of gpta0 in32 i in32 line of gpta1 out32 o1 out32 line of gpta0 out32 o2 out32 line of gpta1 out0 o3 out0 line of ltca2 af11 p4.9 i/o0 a1/ pu port 4 general purpose i/o line 9 in33 i in33 line of gpta0 in33 i in33 line of gpta1 out33 o1 out33 line of gpta0 out33 o2 out33 line of gpta1 out1 o3 out1 line of ltca2 af12 p4.10 i/o0 a1/ pu port 4 general purpose i/o line 10 in34 i in34 line of gpta0 in34 i in34 line of gpta1 out34 o1 out34 line of gpta0 out34 o2 out34 line of gpta1 out2 o3 out2 line of ltca2 ad13 p4.11 i/o0 a1/ pu port 4 general purpose i/o line 11 in35 i in35 line of gpta0 in35 i in35 line of gpta1 out35 o1 out35 line of gpta0 out35 o2 out35 line of gpta1 out3 o3 out3 line of ltca2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 82 v1.1, 2009-04 ac14 p4.12 i/o0 a1/ pu port 4 general purpose i/o line 12 in36 i in36 line of gpta0 in36 i in36 line of gpta1 out36 o1 out36 line of gpta0 out36 o2 out36 line of gpta1 out4 o3 out4 line of ltca2 ae13 p4.13 i/o0 a1/ pu port 4 general purpose i/o line 13 in37 i in37 line of gpta0 in37 i in37 line of gpta1 out37 o1 out37 line of gpta0 out37 o2 out37 line of gpta1 out5 o3 out5 line of ltca2 af13 p4.14 i/o0 a1/ pu port 4 general purpose i/o line 14 in38 i in38 line of gpta0 in38 i in38 line of gpta1 out38 o1 out38 line of gpta0 out38 o2 out38 line of gpta1 out6 o3 out6 line of ltca2 ad14 p4.15 i/o0 a1/ pu port 4 general purpose i/o line 15 in39 i in39 line of gpta0 in39 i in39 line of gpta1 out39 o1 out39 line of gpta0 out39 o2 out39 line of gpta1 out7 o3 out7 line of ltca2 port 5 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 83 v1.1, 2009-04 b13 p5.0 i/o0 a2/ pu port 5 general purpose i/o line 0 rxd0a i asc0 receiver input/output a rxd0a o1 asc0 receiver input/output a out72 o2 out72 line of gpta0 out72 o3 out72 line of gpta1 a13 p5.1 i/o0 a2/ pu port 5 general purpose i/o line 1 txd0 o1 asc0 transmitter output a out73 o2 out73 line of gpta0 out73 o3 out73 line of gpta1 a14 p5.2 i/o0 a2/ pu port 5 general purpose i/o line 2 rxd1a i asc1 receiver input/output a rxd1a o1 asc1 receiver input/output a out74 o2 out74 line of gpta0 out74 o3 out74 line of gpta1 b14 p5.3 i/o0 a2/ pu port 5 general purpose i/o line 3 txd1 o1 asc1 transmitter output a out75 o2 out75 line of gpta0 out75 o3 out75 line of gpta1 c15 p5.4 i/o0 a2/ pu port 5 general purpose i/o line 4 en00 o1 msc0 device select output 0 rready0b o2 mli0 receive channel ready output b out76 o3 out76 line of gpta0 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 84 v1.1, 2009-04 c14 p5.5 i/o0 a2/ pu port 5 general purpose i/o line 5 sdi0 i msc0 serial data input out77 o1 out77 line of gpta0 out77 o2 out77 line of gpta1 out101 o3 out101 line of ltca2 b15 p5.6 i/o0 a2/ pu port 5 general purpose i/o line 6 en10 o1 msc1 device select output 0 tvalid0b o2 mli0 transmit cha nnel valid output b out78 o3 out78 line of gpta0 a15 p5.7 i/o0 a2/ pu port 5 general purpose i/o line 7 sdi1 i msc1 serial data input out79 o1 out79 line of gpta0 out79 o2 out79 line of gpta1 out103 o3 out103 line of ltca2 d17 p5.8 i/o0 f/ pu port 5 general purpose i/o line 8 son0 o1 msc0 differential driver serial data output negative out80 o2 out80 line of gpta0 out80 o3 out 80 line of gpta1 c16 p5.9 i/o0 f/ pu port 5 general purpose i/o line 9 sop0a o1 msc0 differential driv er serial data output positive a out81 o2 out81 line of gpta0 out81 o3 out81 line of gpta1 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 85 v1.1, 2009-04 c17 p5.10 i/o0 f/ pu port 5 general purpose i/o line 10 fcln0 o1 msc0 differential driver clock output negative out82 o2 out82 line of gpta0 out82 o3 out82 line of gpta1 c18 p5.11 i/o0 f/ pu port 5 general purpose i/o line 11 fclp0a o1 msc0 differential driver clock output positive a out83 o2 out83 line of gpta0 out83 o3 out83 line of gpta1 a16 p5.12 i/o0 f/ pu port 5 general purpose i/o line 12 son1 o1 msc1 differential driver serial data outputnegative out84 o2 out84 line of gpta0 out84 o3 out84 line of gpta1 b16 p5.13 i/o0 f/ pu port 5 general purpose i/o line 13 sop1a o1 msc1 differential driv er serial data output positive a out85 o2 out85 line of gpta0 out85 o3 out85 line of gpta1 b17 p5.14 i/o0 f/ pu port 5 general purpose i/o line 14 fcln1 o1 msc1 differential driver clock output negative out86 o2 out86 line of gpta0 out86 o3 out86 line of gpta1 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 86 v1.1, 2009-04 a17 p5.15 i/o0 f/ pu port 5 general purpose i/o line 15 fclnp1a o1 msc1 differential driver clock output positive a out87 o2 out87 line of gpta0 out87 o3 out87 line of gpta1 port 6 f3 p6.4 i/o0 a2/ pu port 6 general purpose i/o line 4 mtsr1 i ssc1 slave receive i nput (slave mode) mtsr1 o1 ssc1 master transmit output (master mode) reserved o2 - reserved o3 - g4 p6.5 i/o0 a2/ pu port 6 general purpose i/o line 5 mrst1 i ssc1 master receive input (master mode) mrst1 o1 ssc1 slave transmit output (slave mode) reserved o2 - reserved o3 - e3 p6.6 i/o0 a2/ pu port 6 general purpose i/o line 6 sclk1 i ssc1 clock input/output sclk1 o1 ssc1 clock input/output reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 87 v1.1, 2009-04 g3 p6.7 i/o0 a2/ pu port 6 general purpose i/o line 7 slsi11 i ssc1 slave select input reserved o1 - reserved o2 - reserved o3 - f4 p6.8 i/o0 a2/ pu port 6 general purpose i/o line 8 rxdcan0 i can node 0 receiver input 0 can node 3 receiver input 1 rxd0b i asc0 receiver input/output b reserved o1 - rxd0b o2 asc0 receiver input/output b reserved o3 - e4 p6.9 i/o0 a2/ pu port 6 general purpose i/o line 9 txdcan0 o1 can node 0 transmitter output txd0 o2 asc0 transmitter output b reserved o3 - f2 p6.10 i/o0 a2/ pu port 6 general purpose i/o line 10 rxdcan1 i can node 1 receiver input 0 can node 0 receiver input 1 rxd1b i asc1 receiver input/output b reserved o1 - rxd1b o2 asc1 receiver input/output b txena o3 e-ray channel a transmit data output enable table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 88 v1.1, 2009-04 e2 p6.11 i/o0 a2/ pu port 6 general purpose i/o line 11 txdcan1 o1 can node 1 transmitter output txd1 o2 asc1 transmitter output b txenb o3 e-ray channel b transmit data output enable e1 p6.12 i/o0 a1/ pu port 6 general purpose i/o line 12 rxdcan2 i can node 2 receiver input 0 can node 1 receiver input 1 rxda1 i e-ray channel a receive data input 1 reserved o1 - reserved o2 - reserved o3 - g2 p6.13 i/o0 a2/ pu port 6 general purpose i/o line 13 txdcan2 o1 can node 2 transmitter output txda o2 e-ray channel a transmit data output reserved o3 - f1 p6.14 i/o0 a1/ pu port 6 general purpose i/o line 14 rxdcan3 i can node 3 receiver input 0 can node 2 receiver input 1 rxdb1 i e-ray channel b receive data input 1 reserved o1 - reserved o2 - reserved o3 - g1 p6.15 i/o0 a2/ pu port 6 general purpose i/o line 15 txdcan3 o1 can node 3 transmitter output txdb o2 e-ray channel b transmit data output reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 89 v1.1, 2009-04 port 7 r3 p7.0 i/o0 a1/ pu port 7 general purpose i/o line 0 req4 i external trigger input 4 ad2emux2 o1 adc2 external multipl exer control output 2 reserved o2 - reserved o3 - r2 p7.1 i/o0 a1/ pu port 7 general purpose i/o line 1 req5 i external trigger input 5 ad0emux2 o1 adc0 external multipl exer control output 2 reserved o2 - reserved o3 - u4 p7.2 i/o0 a1/ pu port 7 general purpose i/o line 2 ad0emux0 o1 adc0 external multipl exer control output 0 reserved o2 - reserved o3 - u3 p7.3 i/o0 a1/ pu port 7 general purpose i/o line 3 ad0emux1 o1 adc0 external multipl exer control output 1 reserved o2 - reserved o3 - t3 p7.4 i/o0 a1/ pu port 7 general purpose i/o line 4 req6 i external trigger input 6 ad2emux0 o1 adc2 external multipl exer control output 0 reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 90 v1.1, 2009-04 t2 p7.5 i/o0 a1/ pu port 7 general purpose i/o line 5 req7 i external trigger input 7 ad2emux1 o1 adc2 external multipl exer control output 1 reserved o2 - reserved o3 - t1 p7.6 i/o0 a1/ pu port 7 general purpose i/o line 6 ad1emux0 o1 adc1 external multipl exer control output 0 reserved o2 - reserved o3 - u2 p7.7 i/o0 a1/ pu port 7 general purpose i/o line 7 ad1emux1 o1 adc1 external multipl exer control output 1 reserved o2 - reserved o3 - port 8 h2 p8.0 i/o0 a2/ pu port 8 general purpose i/o line 0 in40 i i/o line of gpta0 in40 i i/o line of gpta1 out40 o1 i/o line of gpta0 out40 o2 i/o line of gpta1 tclk1 o3 mli1 transmit channel clock output table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 91 v1.1, 2009-04 h1 p8.1 i/o0 a1/ pu port 8 general purpose i/o line 1 in41 i i/o line of gpta0 in41 i i/o line of gpta1 tready1a i mli1 transmit cha nnel ready input a out41 o1 i/o line of gpta0 out41 o2 i/o line of gpta1 reserved o3 - j3 p8.2 i/o0 a2/ pu port 8 general purpose i/o line 2 in42 i i/o line of gpta0 in42 i i/o line of gpta1 out42 o1 i/o line of gpta0 out42 o2 i/o line of gpta1 tvalid1a o3 mli1 transmit cha nnel valid output a j2 p8.3 i/o0 a2/ pu port 8 general purpose i/o line 3 in43 i i/o line of gpta0 in43 i i/o line of gpta1 out43 o1 i/o line of gpta0 out43 o2 i/o line of gpta1 tdata1 o3 mli1 transmit cha nnel data output a j1 p8.4 i/o0 a1/ pu port 8 general purpose i/o line 4 in44 i i/o line of gpta0 in44 i i/o line of gpta1 rclk1a i mli1 receive cha nnel clock input a out44 o1 i/o line of gpta0 out44 o2 i/o line of gpta1 reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 92 v1.1, 2009-04 k2 p8.5 i/o0 a2/ pu port 8 general purpose i/o line 5 in45 i i/o line of gpta0 in45 i i/o line of gpta1 out45 o1 i/o line of gpta0 out45 o2 i/o line of gpta1 rready1a o3 mli1 receive channel ready output a k3 p8.6 i/o0 a1/ pu port 8 general purpose i/o line 6 in46 i i/o line of gpta0 in46 i i/o line of gpta1 rvalid1a i mli1 receive cha nnel valid input a out46 o1 i/o line of gpta0 out46 o2 i/o line of gpta1 reserved o3 - k1 p8.7 i/o0 a1/ pu port 8 general purpose i/o line 7 in47 i i/o line of gpta0 in47 i i/o line of gpta1 rdata1a i mli1 receive cha nnel data input a out47 o1 i/o line of gpta0 out47 o2 i/o line of gpta1 reserved o3 - port 9 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 93 v1.1, 2009-04 a19 p9.0 i/o0 a2/ pu port 9 general purpose i/o line 0 in48 i i/o line of gpta0 in48 i i/o line of gpta1 out48 o1 i/o line of gpta0 out48 o2 i/o line of gpta1 en12 o3 msc1 device select output 2 b19 p9.1 i/o0 a2/ pu port 9 general purpose i/o line 1 in49 i i/o line of gpta0 in49 i i/o line of gpta1 out49 o1 i/o line of gpta0 out49 o2 i/o line of gpta1 en11 o3 msc1 device select output 1 b20 p9.2 i/o0 a2/ pu port 9 general purpose i/o line 2 in50 i i/o line of gpta0 in50 i i/o line of gpta1 out50 o1 i/o line of gpta0 out50 o2 i/o line of gpta1 sop1b o3 msc1 serial data output a20 p9.3 i/o0 a2/ pu port 9 general purpose i/o line 3 in51 i i/o line of gpta0 in51 i i/o line of gpta1 out51 o1 i/o line of gpta0 out51 o2 i/o line of gpta1 fclp1b o3 msc1 clock output table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 94 v1.1, 2009-04 d18 p9.4 i/o0 a2/ pu port 9 general purpose i/o line 4 in52 i i/o line of gpta0 in52 i i/o line of gpta1 out52 o1 i/o line of gpta0 out52 o2 i/o line of gpta1 en03 o3 msc0 device select output 3 ?d19 p9.5 i/o0 a2/ pu port 9 general purpose i/o line 5 in53 i i/o line of gpta0 in53 i i/o line of gpta1 out53 o1 i/o line of gpta0 out53 o2 i/o line of gpta1 en02 o3 msc0 device select output 2 c19 p9.6 i/o0 a2/ pu port 9 general purpose i/o line 6 in54 i i/o line of gpta0 in54 i i/o line of gpta1 out54 o1 i/o line of gpta0 out54 o2 i/o line of gpta1 en01 o3 msc0 device select output 1 d20 p9.7 i/o0 a2/ pu port 9 general purpose i/o line 7 in55 i i/o line of gpta0 in55 i i/o line of gpta1 out55 o1 i/o line of gpta0 out55 o2 i/o line of gpta1 sop0b o3 msc0 serial data output table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 95 v1.1, 2009-04 c20 p9.8 i/o0 a2/ pu port 9 general purpose i/o line 8 fclp0b o1 msc0 clock output fclp0b o2 msc0 clock output fclp0b o3 msc0 clock output a21 p9.9 i/o0 a1/ pu port 9 general purpose i/o line 9 reserved o1 - reserved o2 - reserved o3 - b21 p9.10 i/o0 a1/ pu port 9 general purpose i/o line 10 emgstop i emergency stop reserved o1 - reserved o2 - reserved o3 - c21 p9.11 i/o0 a1/ pu port 9 general purpose i/o line 11 reserved o1 - reserved o2 - reserved o3 - d21 p9.12 i/o0 a1/ pu port 9 general purpose i/o line 12 reserved o1 - reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 96 v1.1, 2009-04 c26 p9.13 i/o0 a2/ pu port 9 general purpose i/o line 13 brkin i ocds break input reserved o1 - reserved o2 - reserved o3 - brkout o ocds break output d26 p9.14 i/o0 a2/ pu port 9 general purpose i/o line 14 brkin i ocds break input reserved o1 - reserved o2 - reserved o3 - brkout o ocds break output port 10 ae15 p10.0 i/o0 a2/ pu port 10 general purpose i/o line 0 mrst0 i ssc0 master receive input (master mode) mrst0 o1 ssc0 slave transmit output (slave mode) reserved o2 - reserved o3 - af15 p10.1 i/o0 a2/ pu port 10 general purpose i/o line 1 mtsr0 i ssc0 slave receive i nput (slave mode) mtsr0 o1 ssc0 master transmit output (master mode) reserved o2 - reserved o3 - table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 97 v1.1, 2009-04 ad15 p10.2 i/o0 a1/ pu port 10 general purpose i/o line 2 slsi01 i ssc0 slave select input reserved o1 - reserved o2 - reserved o3 - af14 p10.3 i/o0 a2/ pu port 10 general purpose i/o line 3 sclk0 i ssc0 clock input/output sclk0 o1 ssc0 clock input/output reserved o2 - reserved o3 - ae14 p10.4 i/o0 a2/ pu port 10 general purpose i/o line 4 slso00 o1 ssc0 slave select output line 0 reserved o2 - reserved o3 - ac15 p10.5 i/o0 a2/ pu port 10 general purpose i/o line 5 slso01 o1 ssc0 slave select output line 1 reserved o2 - reserved o3 - port 11 j26 p11.0 i/o0 b1/ pu port 11 general purpose i/o line 0 reserved o1 - reserved o2 - reserved o3 - a0 o ebu address bus line 0 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 98 v1.1, 2009-04 k25 p11.1 i/o0 b1/ pu port 11 general purpose i/o line 1 reserved o1 - reserved o2 - reserved o3 - a1 o ebu address bus line 1 k26 p11.2 i/o0 b1/ pu port 11 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - a2 o ebu address bus line 2 j23 p11.3 i/o0 b1/ pu port 11 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - a3 o ebu address bus line 3 k24 p11.4 i/o0 b1/ pu port 11 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - a4 o ebu address bus line 4 l25 p11.5 i/o0 b1/ pu port 11 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - a5 o ebu address bus line 5 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 99 v1.1, 2009-04 l26 p11.6 i/o0 b1/ pu port 11 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - a6 o ebu address bus line 6 k23 p11.7 i/o0 b1/ pu port 11 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - a7 o ebu address bus line 7 m26 p11.8 i/o0 b1/ pu port 11 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - a8 o ebu address bus line 8 m25 p11.9 i/o0 b1/ pu port 11 general purpose i/o line 9 reserved o1 - reserved o2 - reserved o3 - a9 o ebu address bus line 9 m24 p11.10 i/o0 b1/ pu port 11 general purpose i/o line 10 reserved o1 - reserved o2 - reserved o3 - a10 o ebu address bus line 10 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 100 v1.1, 2009-04 l24 p11.11 i/o0 b1/ pu port 11 general purpose i/o line 11 reserved o1 - reserved o2 - reserved o3 - a11 o ebu address bus line 11 n26 p11.12 i/o0 b1/ pu port 11 general purpose i/o line 12 reserved o1 - reserved o2 - reserved o3 - a12 o ebu address bus line 12 n23 p11.13 i/o0 b1/ pu port 11 general purpose i/o line 13 reserved o1 - reserved o2 - reserved o3 - a13 o ebu address bus line 13 n24 p11.14 i/o0 b1/ pu port 11 general purpose i/o line 14 reserved o1 - reserved o2 - reserved o3 - a14 o ebu address bus line 14 n25 p11.15 i/o0 b1/ pu port 11 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - a15 o ebu address bus line 15 port 12 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 101 v1.1, 2009-04 p26 p12.0 i/o0 b1/ pu port 12 general purpose i/o line 0 reserved o1 - reserved o2 - reserved o3 - a16 o ebu address bus line 16 p24 p12.1 i/o0 b1/ pu port 12 general purpose i/o line 1 reserved o1 - reserved o2 - reserved o3 - a17 o ebu address bus line 17 p25 p12.2 i/o0 b1/ pu port 12 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - a18 o ebu address bus line 18 r24 p12.3 i/o0 b1/ pu port 12 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - a19 o ebu address bus line 19 r26 p12.4 i/o0 b1/ pu port 12 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - a20 o ebu address bus line 20 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 102 v1.1, 2009-04 r25 p12.5 i/o0 b1/ pu port 12 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - a21 o ebu address bus line 21 j24 p12.6 i/o0 b1/ pu port 12 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - a22 o ebu address bus line 22 j25 p12.7 i/o0 b1/ pu port 12 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - a23 o ebu address bus line 23 port 13 t26 p13.0 i/o0 b1/ pu port 13 general purpose i/o line 0 ad0 i ebu address/data bus line 0 out88 o1 out88 line of gpta0 out88 o2 out88 line of gpta1 out80 o3 out80 line of ltca2 ad0 o ebu address/data bus line 0 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 103 v1.1, 2009-04 t24 p13.1 i/o0 b1/ pu port 13 general purpose i/o line 1 ad1 i ebu address/data bus line 1 out89 o1 out89 line of gpta0 out89 o2 out89 line of gpta1 out81 o3 out81 line of ltca2 ad1 o ebu address/data bus line 1 u26 p13.2 i/o0 b1/ pu port 13 general purpose i/o line 2 ad2 i ebu address/data bus line 2 out90 o1 out90 line of gpta0 out90 o2 out90 line of gpta1 out82 o3 out82 line of ltca2 ad2 o ebu address/data bus line 2 t25 p13.3 i/o0 b1/ pu port 13 general purpose i/o line 3 ad3 i ebu address/data bus line 3 out91 o1 out91 line of gpta0 out91 o2 out91 line of gpta1 out83 o3 out83 line of ltca2 ad3 o ebu address/data bus line 3 v26 p13.4 i/o0 b1/ pu port 13 general purpose i/o line 4 ad4 i ebu address/data bus line 4 out92 o1 out92 line of gpta0 out92 o2 out92 line of gpta1 out84 o3 out84 line of ltca2 ad4 o ebu address/data bus line 4 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 104 v1.1, 2009-04 u25 p13.5 i/o0 b1/ pu port 13 general purpose i/o line 5 ad5 i ebu address/data bus line 5 out93 o1 out93 line of gpta0 out93 o2 out93 line of gpta1 out85 o3 out85 line of ltca2 ad5 o ebu address/data bus line 5 u23 p13.6 i/o0 b1/ pu port 13 general purpose i/o line 6 ad6 i ebu address/data bus line 6 out94 o1 out94 line of gpta0 out94 o2 out94 line of gpta1 out86 o3 out86 line of ltca2 ad6 o ebu address/data bus line 6 w26 p13.7 i/o0 b1/ pu port 13 general purpose i/o line 7 ad7 i ebu address/data bus line 7 out95 o1 out95 line of gpta0 out95 o2 out95 line of gpta1 out87 o3 out87 line of ltca2 ad7 o ebu address/data bus line 7 v25 p13.8 i/o0 b1/ pu port 13 general purpose i/o line 8 ad8 i ebu address/data bus line 8 out96 o1 out96 line of gpta0 out96 o2 out96 line of gpta1 out88 o3 out88 line of ltca2 ad8 o ebu address/data bus line 8 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 105 v1.1, 2009-04 u24 p13.9 i/o0 b1/ pu port 13 general purpose i/o line 9 ad9 i ebu address/data bus line 9 out97 o1 out97 line of gpta0 out97 o2 out97 line of gpta1 out89 o3 out89 line of ltca2 ad9 o ebu address/data bus line 9 y26 p13.10 i/o0 b1/ pu port 13 general purpose i/o line 10 ad10 i ebu address/data bus line 10 out98 o1 out98 line of gpta0 out98 o2 out98 line of gpta1 out90 o3 out90 line of ltca2 ad10 o ebu address/data bus line 10 aa26 p13.11 i/o0 b1/ pu port 13 general purpose i/o line 11 ad11 i ebu address/data bus line 11 out99 o1 out99 line of gpta0 out99 o2 out99 line of gpta1 out91 o3 out91 line of ltca2 ad11 o ebu address/data bus line 11 w25 p13.12 i/o0 b1/ pu port 13 general purpose i/o line 12 ad12 i ebu address/data bus line 12 out100 o1 out100 line of gpta0 out100 o2 out100 line of gpta1 out92 o3 out92 line of ltca2 ad12 o ebu address/data bus line 12 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 106 v1.1, 2009-04 v24 p13.13 i/o0 b1/ pu port 13 general purpose i/o line 13 ad13 i ebu address/data bus line 13 out101 o1 out101 line of gpta0 out101 o2 out101 line of gpta1 out93 o3 out93 line of ltca2 ad13 o ebu address/data bus line 13 y25 p13.14 i/o0 b1/ pu port 13 general purpose i/o line 14 ad14 i ebu address/data bus line 14 out102 o1 out102 line of gpta0 out102 o2 out102 line of gpta1 out94 o3 out94 line of ltca2 ad14 o ebu address/data bus line 14 ab26 p13.15 i/o0 b1/ pu port 13 general purpose i/o line 15 ad15 i ebu address/data bus line 15 out103 o1 out103 line of gpta0 out103 o2 out103 line of gpta1 out95 o3 out95 line of ltca2 ad15 o ebu address/data bus line 15 port 14 w24 p14.0 i/o0 b1/ pu port 14 general purpose i/o line 0 ad16 i ebu address/data bus line 16 out96 o1 out96 line of gpta0 out96 o2 out96 line of gpta1 out96 o3 out96 line of ltca2 ad16 o ebu address/data bus line 16 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 107 v1.1, 2009-04 aa25 p14.1 i/o0 b1/ pu port 14 general purpose i/o line 1 ad17 i ebu address/data bus line 17 out97 o1 out97 line of gpta0 out97 o2 out97 line of gpta1 out97 o3 out97 line of ltca2 ad17 o ebu address/data bus line 17 y24 p14.2 i/o0 b1/ pu port 14 general purpose i/o line 2 ad18 i ebu address/data bus line 18 out98 o1 out98 line of gpta0 out98 o2 out98 line of gpta1 out98 o3 out98 line of ltca2 ad18 o ebu address/data bus line 18 aa23 p14.3 i/o0 b1/ pu port 14 general purpose i/o line 3 ad19 i ebu address/data bus line 19 out99 o1 out99 line of gpta0 out99 o2 out99 line of gpta1 out99 o3 out99 line of ltca2 ad19 o ebu address/data bus line 19 ab25 p14.4 i/o0 b1/ pu port 14 general purpose i/o line 4 ad20 i ebu address/data bus line 20 out100 o1 out100 line of gpta0 out100 o2 out100 line of gpta1 out100 o3 out100 line of ltca2 ad20 o ebu address/data bus line 20 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 108 v1.1, 2009-04 ab24 p14.5 i/o0 b1/ pu port 14 general purpose i/o line 5 ad21 i ebu address/data bus line 21 out101 o1 out101 line of gpta0 out101 o2 out101 line of gpta1 out101 o3 out101 line of ltca2 ad21 o ebu address/data bus line 21 aa24 p14.6 i/o0 b1/ pu port 14 general purpose i/o line 6 ad22 i ebu address/data bus line 22 out102 o1 out102 line of gpta0 out102 o2 out102 line of gpta1 out102 o3 out102 line of ltca2 ad22 o ebu address/data bus line 22 ac26 p14.7 i/o0 b1/ pu port 14 general purpose i/o line 7 ad23 i ebu address/data bus line 23 out103 o1 out103 line of gpta0 out103 o2 out103 line of gpta1 out103 o3 out103 line of ltca2 ad23 o ebu address/data bus line 23 ad26 p14.8 i/o0 b1/ pu port 14 general purpose i/o line 8 ad24 i ebu address/data bus line 24 out104 o1 out104 line of gpta0 out104 o2 out104 line of gpta1 out104 o3 out104 line of ltca2 ad24 o ebu address/data bus line 24 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 109 v1.1, 2009-04 ac25 p14.9 i/o0 b1/ pu port 14 general purpose i/o line 9 ad25 i ebu address/data bus line 25 out105 o1 out105 line of gpta0 out105 o2 out105 line of gpta1 out105 o3 out105 line of ltca2 ad25 o ebu address/data bus line 25 ae26 p14.10 i/o0 b1/ pu port 14 general purpose i/o line 10 ad26 i ebu address/data bus line 26 out106 o1 out106 line of gpta0 out106 o2 out106 line of gpta1 out106 o3 out106 line of ltca2 ad26 o ebu address/data bus line 26 ad25 p14.11 i/o0 b1/ pu port 14 general purpose i/o line 11 ad27 i ebu address/data bus line 27 out107 o1 out107 line of gpta0 out107 o2 out107 line of gpta1 out107 o3 out107 line of ltca2 ad27 o ebu address/data bus line 27 ac24 p14.12 i/o0 b1/ pu port 14 general purpose i/o line 12 ad28 i ebu address/data bus line 28 out108 o1 out108 line of gpta0 out108 o2 out108 line of gpta1 out108 o3 out108 line of ltca2 ad28 o ebu address/data bus line 28 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 110 v1.1, 2009-04 ae25 p14.13 i/o0 b1/ pu port 14 general purpose i/o line 13 ad29 i ebu address/data bus line 29 out109 o1 out109 line of gpta0 out109 o2 out109 line of gpta1 out109 o3 out109 line of ltca2 ad29 o ebu address/data bus line 29 ae24 p14.14 i/o0 b1/ pu port 14 general purpose i/o line 14 ad30 i ebu address/data bus line 30 out110 o1 out110 line of gpta0 out110 o2 out110 line of gpta1 out110 o3 out110 line of ltca2 ad30 o ebu address/data bus line 30 ad24 p14.15 i/o0 b1/ pu port 14 general purpose i/o line 15 ad31 i ebu address/data bus line 31 out111 o1 out111 line of gpta0 out111 o2 out111 line of gpta1 out111 o3 out111 line of ltca2 ad31 o ebu address/data bus line 31 port 15 ae21 p15.0 i/o0 b1/ pu port 15 general purpose i/o line 0 reserved o1 - reserved o2 - reserved o3 - cs0 o chip select output line 0 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 111 v1.1, 2009-04 ad21 p15.1 i/o0 b1/ pu port 15 general purpose i/o line 1 reserved o1 - reserved o2 - reserved o3 - cs1 o chip select output line 1 ad20 p15.2 i/o0 b1/ pu port 15 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - cs2 o chip select output line 2 ad19 p15.3 i/o0 b1/ pu port 15 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - cs3 o chip select output line 3 ae17 p15.4 i/o0 b1/ pu port 15 general purpose i/o line 4 reserved o1 - reserved o2 - reserved o3 - bc0 o byte control line 0 ad17 p15.5 i/o0 b1/ pu port 15 general purpose i/o line 5 reserved o1 - reserved o2 - reserved o3 - bc1 o byte control line 1 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 112 v1.1, 2009-04 af18 p15.6 i/o0 b1/ pu port 15 general purpose i/o line 6 reserved o1 - reserved o2 - reserved o3 - bc2 o byte control line 2 ae18 p15.7 i/o0 b1/ pu port 15 general purpose i/o line 7 reserved o1 - reserved o2 - reserved o3 - bc3 o byte control line 3 af20 p15.8 i/o0 b1/ pu port 15 general purpose i/o line 8 reserved o1 - reserved o2 - reserved o3 - rd o read control line af21 p15.9 i/o0 b1/ pu port 15 general purpose i/o line 9 reserved o1 - reserved o2 - reserved o3 - rd/wr o write control line af22 p15.10 i/o0 b1/ pu port 15 general purpose i/o line 10 reserved o1 - reserved o2 - reserved o3 - adv o address valid output table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 113 v1.1, 2009-04 ae20 p15.11 i/o0 b1/ pu port 15 general purpose i/o line 11 wait i wait input for inse rting wait-states reserved o1 - reserved o2 - reserved o3 - af19 p15.12 i/o0 b1/ pu port 15 general purpose i/o line 12 reserved o1 - reserved o2 - reserved o3 - mr/w o motorola-style read/w rite control signal af23 p15.13 i/o0 b1/ pu port 15 general purpose i/o line 13 reserved o1 - reserved o2 - reserved o3 - baa o burst address advance output af24 p15.14 i/o0 b1/ pu port 15 general purpose i/o line 14 bfclki i burst flash clock i nput (clock feedback). reserved o1 - reserved o2 - reserved o3 - af25 p15.15 i/o0 b2/ pu port 15 general purpose i/o line 15 reserved o1 - reserved o2 - reserved o3 - bfclko o burst mode flash clock output (non- differential) table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 114 v1.1, 2009-04 port 16 af17 p16.0 i/o0 b1/ pu port 16 general purpose i/o line 0 hold i hold request input reserved o1 - reserved o2 - reserved o3 - ad18 p16.1 i/o0 b1/ pu port 16 general purpose i/o line 1 hlda i hold acknowledge output reserved o1 - reserved o2 - reserved o3 - hlda o hold acknowledge output ad22 p16.2 i/o0 b1/ pu port 16 general purpose i/o line 2 reserved o1 - reserved o2 - reserved o3 - breq o bus request output ae19 p16.3 i/o0 b1/ pu port 16 general purpose i/o line 3 reserved o1 - reserved o2 - reserved o3 - cscomb o combined chip select output analog input port ae1 an0 i d analog input 0 ad2 an1 i d analog input 1 aa4 an2 i d analog input 2 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 115 v1.1, 2009-04 ab3 an3 i d analog input 3 ac2 an4 i d analog input 4 aa3 an5 i d analog input 5 ad1 an6 i d analog input 6 ab4 an7 i d analog input 7 ac1 an8 i d analog input 8 ab2 an9 i d analog input 9 y3 an10 i d analog input 10 aa2 an11 i d analog input 11 ab1 an12 i d analog input 12 w3 an13 i d analog input 13 y2 an14 i d analog input 14 aa1 an15 i d analog input 15 v4 an16 i d analog input 16 w2 an17 i d analog input 17 y1 an18 i d analog input 18 v3 an19 i d analog input 19 w1 an20 i d analog input 20 v2 an21 i d analog input 21 v1 an22 i d analog input 22 u1 an23 i d analog input 23 ac8 an24 i d analog input 24 ad8 an25 i d analog input 25 ac7 an26 i d analog input 26 ad7 an27 i d analog input 27 ae6 an28 i d analog input 28 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 116 v1.1, 2009-04 af6 an29 i d analog input 29 ae7 an30 i d analog input 30 af7 an31 i d analog input 31 ac3 an32 i d analog input 32 ae2 an33 i d analog input 33 ad3 an34 i d analog input 34 ad5 an35 i d analog input 35 ae3 an36 i d analog input 36 af2 an37 i d analog input 37 ac4 an38 i d analog input 38 af3 an39 i d analog input 39 ad4 an40 i d analog input 40 ae4 an41 i d analog input 41 ac5 an42 i d analog input 42 af4 an43 i d analog input 43 system i/o b22 porst i input only/ pd power-on reset input (input pad with input spike-filter) a23 esr0 i/o a2 external system re quest reset input 0 default configuration duri ng and after reset is open-drain driver, corres ponding to a2 strong driver, sharp edge. the driver drives low during power-on reset. a22 esr1 i/o a2/ pd external system re quest reset input 1 e24 tck i input only/ pd jtag module clock input dap0 i device access port line 0 table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 117 v1.1, 2009-04 e25 tdi i a2/ pu jtag module serial data input brkin i ocds break input (alternate output) brkout o ocds break output (alternate input) b23 testmode i input only/ pu test mode select input f24 tms i a2/ pd jtag module state machine control input dap1 i/o device access port line 1 f23 trst i input only/ pd jtag module reset/enable input g26 xtal1 i main oscillator/pll/clock generator input g25 xtal2 o main oscillator/pll/clock generator output d25 tdo o a2/ pu jtag module serial data output brkin i ocds break input (alternate input) brkout o ocds break output (alternate output) dap2 o device access port line 2 a1, af1, af26, a24, c22, ac21, ad23, ae22, ae23 n.c. - - not connected. these pins ar e reserved for future extension and sh all not be connected externally. power supply w4 v ddm - - adc analog part powe r supply (3.3v - 5v) y4 v ssm - - adc analog part ground ae5 v aref0 - - adc0 reference voltage table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 118 v1.1, 2009-04 af5 v agnd0 - - adc0 reference ground v agnd2 - - adc2 reference ground ad6 v aref1 - - adc1 reference voltage ac6 v agnd1 - - adc1 reference ground ad9 v aref2 - - adc2 reference voltage af8 v faref - - fadc reference voltage ae8 v fagnd - - fadc reference ground ae9 v ddmf - - fadc analog part power supply (3.3v) 1) ac9 v ddaf - - fadc analog part logic power supply (1.5v) af9 v ssmf - - fadc analog part ground v ssaf - - fadc analog part logic ground a18, b18, h3 v ddfl3 - - flash power supply (3.3v) f25 v ssosc - - main oscillator ground v ss - - digital ground f26 v ddosc - - main oscillator po wer supply (1.5v) e26 v ddosc3 - - main oscillator po wer supply (3.3v) g23 v ddpf - - e-ray pll power supply (1.5v) g24 v ddpf3 - - e-ray pll power supply (3.3v) table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 119 v1.1, 2009-04 ac11, ac20, ab23, v23, p23, e23, d24, c25, b26, d16, d9, h4, r4 v dd - - digital core power supply (1.5v) ac16, ad16, ae16, af16, d22, c23, b24, a25, d14, d7, k4 v ddp - - port power supply (3.3v) h23, h24, h25, h26, m23, t23, y23, ac18, ac22 v ddebu - - ebu port power supply (2.5v - 3.3v) r1 v dde(sb) - - emulation stand-by sram power supply (1.5v) (emulation device only) note: this pin is n.c. in a productive device. table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 120 v1.1, 2009-04 ac10, ac17, ac19, ac23, w23, r23, l23, d23, c24, b25, a26, d15, d8, j4, t4 v ss - - digital ground (outer balls) k10, k11, k12, k13, k14, k15, k16, k17 v ss - - digital ground (center balls) l10, l11, l12, l13, l14, l15, l16, l17 v ss - - digital ground (center balls cont?d) m10, m11, m12, m13, m14, m15, m16, m17 v ss - - digital ground (center balls cont?d) table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 121 v1.1, 2009-04 n10, n11, n12, n13, n14, n15, n16, n17 v ss - - digital ground (center balls cont?d) p10, p11, p12, p13, p14, p15, p16, p17 v ss - - digital ground (center balls cont?d) r10, r11, r12, r13, r14, r15, r16, r17 v ss - - digital ground (center balls cont?d) t10, t11, t12, t13, t14, t15, t16, t17 v ss - - digital ground (center balls cont?d) table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 122 v1.1, 2009-04 legend for table 4 column ? ctrl. ?: i = input (for gpio port lines with iocr bit field sele ction pcx = 0xxx b ) o = output o0 = output with iocr bit fi eld selection pcx = 1x00 b o1 = output with iocr bit fi eld selection pcx = 1x01 b (alt1) o2 = output with iocr bit fi eld selection pcx = 1x10 b (alt2) o3 = output with iocr bit fi eld selection pcx = 1x11 b (alt3) column ? type ?: a1 = pad class a1 (lvttl) a2 = pad class a2 (lvttl) f = pad class f (lvds/cmos) d = pad class d (adc) pu = with pull-up device co nnected during reset ( porst = 0) pd = with pull-down device c onnected during reset ( porst = 0) tr = tri-state during reset ( porst = 0) 3.1.2 pull-up/pull-down r eset behavior of the pins u10, u11, u12, u13, u14, u15, u16, u17 v ss - - digital ground (center balls cont?d) 1) this pin is also connected to the analog power supply for comparator of the adc module. table 5 list of pull-up/pull-down reset behavior of the pins pins porst = 0 porst = 1 all gpios, tdi, testmode pull-up porst, trst , tck, tms pull-down table 4 pin definitions and functions (bga-416 package) (cont?d) pin symbol ctrl. type function www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 pinning data sheet 123 v1.1, 2009-04 esr0 the open-drain driver is used to drive low. 1) pull-up 2) esr1 pull-down 2) tdo pull-up high-impedance 1) valid additionally after deactivation of porst until the internal reset phase has finished. see the scu chapter for details. 2) see the scu_iocr register description. table 5 list of pull-up/pull-down reset behavior of the pins pins porst = 0 porst = 1 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 identification registers data sheet 4-124 v1.1, 2009-04 4 identification registers the identification register s uniquely identify a module or the whole device. table 4-1 TC1797 identification registers 1) short name value address stepping adc0_id 0059 c000 h f010 1008 h ? adc1_id 0059 c000 h f010 1408 h ? adc2_id 0059 c000 h f010 1808 h ? asc0_id 0000 4402 h f000 0a08 h ? asc1_id 0000 4402 h f000 0b08 h ? can_id 002b c051 h f000 4008 h ? cbs_jdpid 0000 6350 h f000 0408 h ? cbs_jtagid 1015 a083 h f000 0464 h ? cps_id 0015 c007 h f7e0 ff08 h ? cpu_id 000a c006 h f7e1 fe18 h ? dma_id 001a c004 h f000 3c08 h ? dmi_id 0008 c005 h f87f fc08 h ? ebu_id 0014 c009 h f800 0008 h ? eray_id 0044 c003 h f001 0008 h ? fadc_id 0027 c003 h f010 0408 h ? flash0_id 0053 c001 h f800 2008 h ? flash1_id 0055 c001 h f800 4008 h ? fpu_id 0054 c003 h f7e1 a020 h ? gpta0_id 0029 c005 h f000 1808 h ? gpta1_id 0029 c005 h f000 2008 h ? lbcu_id 000f c005 h f87f fe08 h ? lfi_id 000c c006 h f87f ff08 h ? ltca2_id 002a c005 h f000 2808 h ? mchk_id 001b c001 h f010 c208 h ? mli0_id 0025 c007 h f010 c008 h ? mli1_id 0025 c007 h f010 c108 h ? msc0_id 0028 c003 h f000 0808 h ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 identification registers data sheet 4-125 v1.1, 2009-04 msc1_id 0028 c003 h f000 0908 h ? pcp_id 0020 c006 h f004 3f08 h ? pmi_id 000b c005 h f87f fd08 h ? pmu0_id 0050 c001 h f800 0508 h ? pmu1_id 0051 c001 h f800 6008 h ? sbcu_id 0000 6a0c h f000 0108 h ? scu_chipid 0000 9001 h f000 0640 h ? scu_id 0052 c001 h f000 0508 h ? scu_manid 0000 1820 h f000 0644 h ? scu_rtid 0000 0003 h f000 0648 h ac only ssc0_id 0000 4511 h f010 0108 h ? ssc1_id 0000 4511 h f010 0208 h ? stm_id 0000 c006 h f000 0208 h ? 1) valid for all design steps except if explicitely defined. table 4-1 TC1797 identification registers (cont?d) 1) short name value address stepping www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 126 v1.1, 2009-04 5 electrical parameters 5.1 general parameters 5.1.1 parameter interpretation the parameters listed in this section partly represent the characteristics of the TC1797 and partly its requirements on the system. to aid interpre ting the parameters easily when evaluating them for a design, they are ma rked with an two-lett er abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the TC1797 and must be rega rded for a system design. ? sr such parameters indicate s ystem r equirements which mu st provided by the microcontroller system in wh ich the TC1797 designed in. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 127 v1.1, 2009-04 5.1.2 pad driver and pad classes summary this section gives an overview on the di fferent pad driver cl asses and its basic characteristics. more details (mainl y dc parameters) are defined in the section 5.2.1 . table 6 pad driver and pad classes overview class power supply type sub class speed grade load leakage 1) 1) values are for t jmax = 150 c. termination a 3.3 v lvttl i/o, lvttl outputs a1 (e.g. gpio) 6 mhz 100 pf 500 na no a2 (e.g. serial i/os) 40 mhz 50 pf 6 a series termination recommended b 2.375 - 3.6 v 2) 2) ac characteristics for ebu pins are valid for 2.5 v 5% and 3.3 v 5%. lvttl i/o b1 (e.g. ext. bus interface) 40 mhz 50 pf 6 a no b2 (e.g. bus clock) 75 mhz 35 pf series termination recommended (for f > 25 mhz) f 3.3 v lvds/ cmos ? 50 mhz ? ? parallel termination 3) , 100 ? 10% 3) in applications where the lvds pins are not used (dis abled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 ? 10%. de 5 v adc ? ? ? ? see table 11 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 128 v1.1, 2009-04 5.1.3 absolute maximum ratings stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the devi ce. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rati ng overload conditions ( v in > related v dd or v in < v ss ) the voltage on the related v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolu te maximum ratings. table 7 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max. ambient temperature t a sr -40 ? 125 c under bias storage temperature t st sr -65 ? 150 c ? junction temperature t j sr -40 ? 150 c under bias voltage at 1.5 v power supply pins with respect to v ss 1) v dd sr ? ? 2.25 v ? voltage at 3.3 v power supply pins with respect to v ss 2) v ddebu v ddp sr ? ? 3.75 v ? voltage at 5 v power supply pins with respect to v ss v ddm sr ? ? 5.5 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.5 ? v ddp + 0.5 or max. 3.7 v whatever is lower voltage on any class b input pin with respect to v ss v in sr -0.5 ? v ddebu + 0.5 or max. 3.7 v whatever is lower voltage on any class d analog input pin with respect to v agnd v ain v arefx sr -0.5 ? v ddm + 0.5 v ? voltage on any shared class d analog input pin with respect to v ssaf , if the fadc is switched thro ugh to the pin. v ainf v faref sr -0.5 ? v ddm + 0.5 v ? cpu frequency f cpu sr ? ? 180 150 mhz derivative dependent www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 129 v1.1, 2009-04 5.1.4 operating conditions the following operating conditions must not be exceed ed in order to ensure correct operation of the TC1797 . all parameters specif ied in the following table refer to these operating conditions, un less otherwise noticed. the following operating conditions must not be exceed ed in order to ensure correct operation of the TC1797 . all parameters specif ied in the following table refer to these operating conditions, un less otherwise noted. pcp frequency f pcp sr ? ? 180 150 mhz derivative dependent e-ray sample frequency f sample sr ? ? 80 mhz 1) applicable for v dd , v ddosc , v ddpf , and v ddaf . 2) applicable for v ddp , v ddebu , v ddfl3, v dpf3, and v ddmf . table 8 operating condition parameters parameter symbol values unit note / test condition min. typ. max. digital supply voltage 1) v dd sr v ddosc sr 1.42 ? 1.58 2) v ? v ddp sr v ddosc3 sr 3.13 ? 3.47 3) v for class a pins (3.3 v 5%) v ddebu sr 3.13 2.375 ? 3.47 3) 2.625 v for class b (ebu) pins v ddfl3 sr 3.13 ? 3.47 3) v ? analog supply voltages v ddmf sr 3.13 ? 3.47 3) v fadc v ddaf sr 1.42 ? 1.58 2) v fadc v ddm sr 4.75 ? 5.25 v for class de pins, adc digital ground voltage v ss sr 0 ? ? v ? ambient temperature under bias t a sr -40 ? +125 c ? table 7 absolute maximu m rating parameters parameter symbol values unit note / test con dition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 130 v1.1, 2009-04 analog supply voltages ? ? ? ? ? see separate specification page 137 , page 142 overload current at class d pins i ov -1 ? 3 ma 4) sum of overload current at class d pins |i ov | ? ? 10 ma per single adc overload coupling factor for analog inputs 5) k ovap ? ? 5 10- 5 0 < i ov < 3 ma k ovan ? ? 5 10- 4 -1 ma< i ov < 0 cpu & lmb bus frequency f cpu sr ? ? 180 150 mhz derivative dependent pcp frequency f pcp sr ? ? 180 150 mhz derivative dependent 6) fpi bus frequency f sys sr ? ? 90 mhz 6) short circuit current i sc sr -5 ? +5 ma 7) absolute sum of short circuit currents of a pin group (see table 9 ) | i sc_pg | sr ? ? 20 ma see note inactive device pin current i id sr -1 ? 1 ma all power supply voltages v ddx = 0 absolute sum of short circuit currents of the device | i sc_d | sr ? ? 100 ma see note 4) external load capacitance c l sr ? ? ? pf depending on pin class. see dc characteristics 1) digital supply voltages applied to the TC1797 must be static regulated voltages wh ich allow a typical voltage swing of 5%. 2) voltage overshoot up to 1.7 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) voltage overshoot to 4 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h table 8 operating condition parameters parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 131 v1.1, 2009-04 4) see additional document ?tc1767 pin reliability in overlo ad? for definition of overload current on digital pins. 5) the overload coupling factor (ka) defines the worst ca se relation of an overload condition (iov) at one pin to the resulting leakage current (ileaktot) into an adjacent pin: ileaktot = ka |iov| + ioz1. thus under overload conditions an additional error l eakage voltage (vael) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (rain). that means vael = rain |ileaktot|. the definition of adjacent pins is re lated to their order on the silicon. the injected leakage current always flows in the opposite direction from the causing overload current. therefore, the total leakage current must be calculated as an algebraic sum of the both component leakage currents (the own leakage current ioz1 and the optional injected leakage current). 6) the pll jitter characteristics add to this value acco rding to the application settings. see the pll jitter parameters. 7) applicable for digital outputs. table 9 pin groups for overload / short-circuit current sum parameter group pins 1 p4.[7:0] 2 p4.[15:8] 3 p10.[5:0] 4 p15.[0, 1, 7:4, 11, 12] 5 p15.[3:0, 8, 13], p16.3 6 p15.9, p16.2, p1 5.10, p15.[15:14] 7 p14.[15:10] 8 p14.[9:8] 9 p14.[7:2] 10 p14.[1:0], p13.[15:14] 11 p13.[13:12] 12 p13.[11:6] 13 p13.[5:2] 14 p13.[1:0], p12[5:4] 15 p12.[3:0] 16 p11.[15:12] 17 p11.[11:8] 18 p11.[7:4] 19 p11.[3:0] 20 p12.[7:6] www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 132 v1.1, 2009-04 21 p9.[14:13, 10:9] 22 p9.[12:11, 8:7, 2] 23 p9.[6:5, 3, 1] 24 p9.[0, 4], p5.[10, 11] 25 p5.[15:14, 9:8] 26 p5.[13:12, 6, 4] 27 p5.[7:5, 3, 0] 28 p3.[7:0] 29 p3.[15:8] 30 p0.[7:0] 31 p0.[15:8] 32 p2.[15:9] 33 p2.[8:4] 34 p2.[3:2], p6[9:8] 35 p6[11, 6:4] 36 p6.[15:12, 10, 7] 37 p8.[7:0] 38 p1.[15:13, 11:8, 5] 39 p1.[12, 7, 6, 4, 3] 40 p1.[1:0], p7.0 41 p7.[5:1] 42 p7.[7:6] table 9 pin groups for overload / short-circuit current sum parameter group pins www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 133 v1.1, 2009-04 5.2 dc parameters 5.2.1 input/output pins table 10 input/output dc-characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. general parameters pull-up current 1) | i puh | cc 10 ? 100 a v in < v ihamin ; class a1/a2/f/input pads. 5 ? 85 a v in < v ihbmin ; class b1/b2 pads. pull-down current 1) | i pdl | cc 10 ? 150 a v in > v ilamax ; class a1/a2/f/input pads. v in > v ilbmax ; class b1/b2 pads pin capacitance 1) (digital i/o) c io cc ? ? 10 pf f = 1 mhz t a = 25 c input only pads ( v ddp = 3.13 to 3.47 v = 3.3 v 5%) input low voltage v ili sr -0.3 ? 0.36 v ddp v ? input high voltage v ihi sr 0.62 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.58 ? ? ? ? input high voltage trst , tck v ihj sr 0.64 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower input hysteresis hysi cc 0.1 v ddp ? ? v 4) input leakage current i ozi cc ? ? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 2) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 134 v1.1, 2009-04 spike filter always blocked pulse duration t sf1 cc ? ? 10 ns spike filter pass- through pulse duration t sf2 cc 100 ? ? ns class a pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage 3) v ola cc ? ? 0.4 v i ol = 2 ma for medium and strong driver mode, i ol = 500 a for weak driver mode output high voltage 2) 3) v oha cc 2.4 ? ? v i oh = -2 ma for medium and strong driver mode, i oh = -500 a for weak driver mode v ddp - 0.4 ? ? v i oh = -1.4 ma for medium and strong driver mode, i oh = -400 a for weak driver mode input low voltage class a1/2 pins v ila sr -0.3 ? 0.36 v ddp v ? input high voltage class a1 pins v iha1 sr 0.62 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih class a1 pins cc 0.58 ? ? ? ? input high voltage class a2 pins v iha2 sr 0.60 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih class a2 pins cc 0.6 ? ? ? ? input hysteresis hysa cc 0.1 v ddp ? ? v 4) table 10 input/output dc-characteristics (cont?d)(operatin g conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 135 v1.1, 2009-04 input leakage current class a2 pins i oza2 cc ? ? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 2) input leakage current class a1 pins i oza1 cc ? ? 500 na 0 v < v in < v ddp class b pads ( v ddebu = 2.375 to 3.47 v) output low voltage v olb cc ? ? 0.4 v i ol = 2 ma output high voltage v ohb cc v ddebu - 0.4 ? ? v i ol = 2 ma input low voltage v ilb sr -0.3 ? 0.34 v ddebu v ? input high voltage v ihb sr 0.64 v ddebu ? v ddebu + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? ? input hysteresis hysb cc 0.1 v ddebu ? ? v 4) input leakage current class b pins i ozb cc ? ? 3000 6000 na (( v ddebu /2)-0.6) < v in < (( v ddebu /2)+0.6) 5) otherwise 2) class f pads, lvds mode ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage v ol cc 875 ? ? mv parallel termination 100 ? 1% output high voltage v oh cc ? 1525 mv parallel termination 100 ? 1% output differential voltage v od cc 150 ? 400 mv parallel termination 100 ? 1% output offset voltage v os cc 1075 ? 1325 mv parallel termination 100 ? 1% output impedance r 0 cc 40 ? 140 ? ? table 10 input/output dc-characteristics (cont?d)(operatin g conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 136 v1.1, 2009-04 class f pads, cmos mode ( v ddp = 3.13 to 3.47 v = 3.3v 5%) input low voltage class f pins v ilf sr -0.3 ? 0.36 v ddp v ? input high voltage class f pins v ihf sr 0.60 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower input hysteresis class f pins hysf cc 0.05 v ddp ? ? v input leakage current class f pins i ozf ? ? 3000 6000 na (( v ddp /2)-1) < v in < (( v ddp /2)+1) otherwise 2) output low voltage 6) v olf cc ? ? 0.4 v i ol = 2 ma output high voltage 2) 6) v ohf cc 2.4 ? ? v i oh = -2 ma v ddp - 0.4 ? ? v i oh = -1.4 ma class d pads see adc characteristics ? ? ? ? ? 1) not subject to production test, verified by design / characterization. 2) only one of these parameters is tested, the other is verified by design characterization 3) maximum resistance of the driver r dson , defined for p_mos / n_mos transistor separately: 25 / 20 ? for strong driver mode, i oh / l < 2 ma, 200 / 150 ? for medium driver mode, i oh / l < 400 ua, 600 / 400 ? for weak driver mode, i oh / l < 100 ua, verified by design / characterization. 4) function verified by design, value verified by design characterization. hysteresis is implemented to avoid metastable st ates and switching due to internal ground bounce. it cannot be guaranteed that it suppresses switching due to external system noise. 5) v ddebu = 2.5 v 5%. for v ddebu = 3.3 5% see class a2 pads. 6) the following constraint applies to an lvds pair us ed in cmos mode: only one pin of a pair should be used as output, the other should be used as input, or both pi ns should be used as inputs. using both pins as outputs is not recommended because of t he higher crosstalk between them. table 10 input/output dc-characteristics (cont?d)(operatin g conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 137 v1.1, 2009-04 5.2.2 analog to digital converters (adc0/adc1/adc2) all adc parameters are optimized for and valid in the range of v ddm = 5v 5%. table 11 adc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. analog supply voltage v ddm sr 4.75 5 5.25 1) v ? 3.13 3.3 3.47 v ? v dd sr 1.42 1.5 1.58 2) v power supply for adc digital part, internal supply analog ground voltage v ssm sr -0.1 ? 0.1 v ? analog reference voltage 16) v arefx sr v agndx +1 v v ddm v ddm + 0.05 1) 3)4) v ? analog reference ground 16) v agndx sr v ssmx - 0.05v 0 v aref - 1v v ? analog input voltage range v ain sr v agndx ? v arefx v ? analog reference voltage range 5) 16) v arefx - v agndx sr v ddm /2 ? v ddm + 0.05 v ? converter clock f adc sr 1 ? 90 mhz ? internal adc clocks f adci cc 0.5 ? 10 mhz ? sample time t s cc 2 ? 257 tad ci ? total unadjusted error 5) tue 6) cc ? ? 4 lsb 12-bit conversion, without noise 7)8) ? ? 2 lsb 10-bit conversion 8) ? ? 1 lsb 8-bit conversion 8) dnl error 9) 5) ea dnl cc ? 1.5 3.0 lsb 12-bit conversion without noise 8) 10) inl error 9) 5) ea inl cc ? 1.5 3.0 lsb 12-bit convesion without noise 8) 10) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 138 v1.1, 2009-04 gain error 9) 5) ea gain cc ? 0.5 3.5 lsb 12-bit conversion without noise 8) 10) offset error 9) 5) ea off cc ? 1.0 4.0 lsb 12-bit converson without noise 8) 10) input leakage current at analog inputs of adc0/1 11) 12) 13) i oz1 cc -300 ? 100 na (0% v ddm ) < v in < (3% v ddm ) -100 ? 200 na (3% v ddm ) < v in < (97% v ddm ) -100 ? 300 na (97% v ddm ) < v in < (100% v ddm ) input leakage current at v aref0/1/2, per module i oz2 cc ? ? 1.5 a 0 v < v aref < v ddm, no conversion running input current at v aref0/1/2 16) , per module i aref cc ? 35 75 a rms 0 v < v aref < v ddm 14) total capacitance of the voltage reference inputs 15)16) c areftot cc ? 20 40 pf 8) switched capacitance at the positive reference voltage input 16) c arefsw cc ? 15 30 pf 8) 17) resistance of the reference voltage input path 15) r aref cc ? 500 1000 ? 500 ohm increased for an[1:0] used as reference input 8) total capacitance of the analog inputs 15) c aintot cc ? 25 30 pf 1) 8) table 11 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 139 v1.1, 2009-04 switched capacitance at the analog voltage inputs c ainsw cc ? 7 20 pf 8) 18) on resistance of the transmission gates in the analog voltage path r ain cc ? 700 1500 ? 8) on resistance for the adc test (pull-down for ain7) r ain7t cc 180 550 900 19) ? test feature available only for ain7 8) 20) current through resistance for the adc test (pull- down for ain7) i ain7t cc ? 15 rms 30 peak ma test feature available only for ain7 8) 1) voltage overshoot to tbd. v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) voltage overshoot to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) if the reference voltage v aref increases or the v ddm decreases, so that v aref = ( v ddm + 0.05 v to v ddm + 0.07v), then the accuracy of the adc decreases by 4lsb12. 5) if a reduced reference voltage in a range of v ddm /2 to v ddm is used, then the adc converter errors increase. if the reference voltage is reduced with the factor k (k<1 ), then tue, dnl, inl gain and offset errors increase with the factor 1/k. if a reduced reference voltage in a range of 1 v to v ddm /2 is used, then there are additional decrease in the adc speed and accuracy. 6) tue is tested at v aref = 5.0 v, v agnd = 0 v and v ddm = 5.0 v 7) adc module capability. 8) not subject to production test, verified by design / characterization. 9) the sum of dnl/inl/gain/offset errors does not exceed the related tue total unadjusted error. 10) for 10-bit conversions the dnl/inl/gain/offset error values must be multiplied with factor 0.25. for 8-bit conversions the dnl/inl/gain/offset error values must be multiplied with 0.0625. 11) the leakage current definition is a continuous function, as shown in figure 20 . the numerical values defined determine the characteristic points of the given continuous linear appr oximation - they do not define step function. table 11 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 140 v1.1, 2009-04 figure 18 adc0/adc1 clock circuit 12) only one of these parameters is tested, the other is verified by design characterization. 13) the leakage current decreases typically 30% for junction temperature decrease of 10oc. 14) i aref_max is valid for the minimum specified conversion ti me. the current flowing during an adc conversion with a duration of up to t c = 25 s can be calculated with the formula i aref_max = q conv / t c . every conversion needs a total charge of q conv = 150 pc from v aref . all adc conversions with a duration longer than t c = 25s consume an i aref_max = 6a. 15) for the definition of the parameters see also figure 19 . 16) applies to ainx, when used as auxiliary reference inputs. 17) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smaller capacitances are successively switched to the reference voltage. 18) the sampling capacity of the conversion c-network is pre-charged to v aref / 2 before the sampling moment. because of the parasitic elements the vo ltage measured at ainx deviates from v aref /2, and is typically 1.35 v. 19) rain7t = 1400 ohm maximum and 830 ohm typical in the v ddm = 3.3 v 5% range. 20) the dc current at the pin is limited to 3 ma for the operational lifetime. table 12 conversion time (operating conditions apply) parameter symbol value unit note conversion time with post-calibration t c cc 2 t adc + (4 + stc + n) t adci s n = 8, 10, 12 for n - bit conversion t adc = 1 / f adc t adci = 1 / f adci conversion time without post-calibration 2 t adc + (2 + stc + n) t adci adc_clocking analog part analog clock f adci digital clock f adcd f adc arbiter divider for f adcd registers interrupts, etc. clock generation divider for f adci adc kernel www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 141 v1.1, 2009-04 figure 19 adc0/adc1 input circuits figure 20 adc0/adc1anal og inputs leakage reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx v in [v ddm % ] 200na 300na 3% 100% 97% ioz1 -300na -100na adc leakage 10.vsd 100na www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 142 v1.1, 2009-04 5.2.3 fast analog to digital converter (fadc) all parameters apply to fadc used in differential mode , which is the default and the intended mode of operation, and which takes ad vantage of many error cancelation effects inherent to differenti al measurements in general. table 13 fadc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dnl error ef dnl cc ? ? 1 lsb 9) inl error ef inl cc ? ? 4 lsb 9) gradient error 9) ef grad cc ? ? 5 % without calibration gain 1, 2, 4 ? ? 6 % without calibration gain 8 offset error 9) 1) ef off 2) cc ? ? 20 3) mv with calibration 1) ? ? 90 3) mv without calibration reference error of internal v faref /2 ef ref cc ? ? 60 mv ? analog supply voltages v ddmf sr 3.13 ? 3.47 4) v ? v ddaf sr 1.42 ? 1.58 5) v ? analog ground voltage v ssaf sr -0.1 ? 0.1 v ? analog reference voltage v faref sr 3.13 ? 3.47 4) 6) v nominal 3.3 v analog reference ground v fagnd sr v ssaf - 0.05 v ? v ssaf + 0.05 v v ? analog input voltage range v ainf sr v fagnd ? v ddmf v ? analog supply currents i ddmf sr ? ? 15 ma ? i ddaf sr ? ? 12 ma 7) input current at v faref i faref cc ? ? 120 a rms independent of conversion input leakage current at v faref 8) i foz2 cc ? ? 500 na 0 v < v in < v ddmf input leakage current at v fagnd 8) i foz3 cc ? ? 8 a 0 v < v in < v ddmf www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 143 v1.1, 2009-04 the calibration procedure should run a fter each power-up, wh en all power supply voltages and the reference volt age have stabilized. the offset calibration must run first, followed by the gain calibration. conversion time t c cc ? ? 21 clk of f adc for 10-bit conv. converter clock f fadc sr ? ? 90 mhz ? input resistance of the analog voltage path (rn, rp) r fain cc 100 ? 200 k ? 9) channel amplifier cutoff frequency 9) f coff cc 2 ? ? mhz ? settling time of a channel amplifier after changing enn or enp 9) t set cc ? ? 5 s ? 1) calibration should be performed at each power-up. in case of continuous operation, calibration should be performed minimum once per week, or on regular basis in order to compensate for temperature changes. 2) the offset error voltage drifts over the whole temperature range maximum 6 lsb. 3) applies when the gain of the channel equals one. for the ot her gain settings, the offset error increases; it must be multiplied with the applied gain. 4) voltage overshoots up to 4 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 5) voltage overshoots up to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 6) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 7) current peaks of up to 40 ma with a duration of max. 2 ns may occur 8) this value applies in power-down mode. 9) not subject to production test, verified by design / characterization. table 13 fadc characteristics (operating conditi ons apply) (cont?d) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 144 v1.1, 2009-04 figure 21 fadc input circuits fadc_inprefdiag = + - + - r n fainxn fainxp v fag nd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fag nd v faref i faref www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 145 v1.1, 2009-04 5.2.4 oscillator pins note: it is strongly recommended to measure the os cillation allow ance (negative resistance) in the final tar get system (layout) to dete rmine the optimal parameters for the oscillator ope ration. please refer to the limits specif ied by the crystal supplier. 5.2.5 temperature sensor table 14 oscillator pins characteristics (operating co nditions apply) parameter symbol values unit note / test condition min. typ. max. frequency range f osc cc 4 ? 40 mhz direct input mode selected 8 ? 25 mhz external crystal mode selected input low voltage at xtal1 1) 1) if the xtal1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 v ddosc3 is necessary. v ilx sr -0.2 ? 0.3 v ddosc3 v ? input high voltage at xtal1 1) v ihx sr 0.7 v ddosc3 ? v ddosc3 + 0.2 v ? input current at xtal1 i ix1 cc ? ? 25 a 0 v < v in < v ddosc3 table 15 temperature sensor characteristics (operating co nditions apply) parameter symbol values unit note / test condition min. typ. max. temperature sensor range t sr sr -40 150 c junction temperature temperature sensor measurement time t tsmt sr ? ? 100 s ? start-up time after reset t tsst sr ? ? 10 s ? sensor accuracy t tsa cc ? ? 6 c calibrated www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 146 v1.1, 2009-04 the following formul a calculates the temperature measured by the dts in [ o c] from the result bitfield of the dtsstat register. (1) tj dtsstat result 619 ? 228 , ----------------- ----------------- ---------------- --------------- - = www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 147 v1.1, 2009-04 5.2.6 power supply current the default test conditions (differences explicitly specified) are: vdd=1.58 v, vdd=3.47 v, fcpu=180 mhz, tj=150oc table 16 power supply currents (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. core active mode supply current 1)2) 3) 1) infineon power loop: cpu and pcp running, all peripherals active. the power consumption of each custom application will most probably be lower than th is value, but must be evaluated separately. 2) the i dd decreases typically by 120 ma if the f cpu decreases by 50 mhz, at constant t j = 150oc, for the infineon max power loop. the dependency in this range is, at constant junction temperature, linear. i dd cc ? ? 600 ma f cpu =180 mhz f cpu / f sys = 2:1 realistic core active mode supply current 4) 5) ? ? 430 ma v dd = 1.53 v, t j = 150 o c e-ray pll 1.5 v supply i ddpf cc ? ? 4 ma ? e-ray pll 3.3 v supply i ddpf3 cc ? ? 5 ma ? 5) fadc 3.3 v analog supply current i ddmf cc ? ? 15 ma ? fadc 1.5 v analog supply current i ddaf cc ? ? 12 ma ? 5) flash memory 3.3 v supply current i ddfl3r cc ? ? 125 ma continuously reading the flash memory 6) i ddfl3e cc ? ? 120 ma flash memory erase-verify 7) oscillator 1.5 v supply i ddosc cc ? ? 3 ma ? 5) oscillator 3.3 v supply i ddosc3 cc ? ? 10 ma ? 5) lvds 3.3 v supply i lvds ? ? 30 ma in total for four pairs pad currents, sum of v ddp 3.3 v supplies i ddp cc ? ? 30 ma ? 5) 8) i ddp_fp cc ? ? 54 ma i ddp including data flash programming current 8) 9) adc 5 v power supply i ddm cc ? ? 6 ma adc0/1/2 maximum average power dissipation 1) p d sr ? ? 1800 mw worst case t a = 125 o c , p d r ja < 25 o c www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 148 v1.1, 2009-04 3) not using the e-ray module, e-ray pll in an applicatio n lowers the current consumption for typically 9ma. 4) the i dd decreases by typically 70 ma if the f cpu is decreased by 50 mhz, at constant t j = 150 o c, for the realistic pattern. the dependency in this range is, at constant junction temperature, linear. 5) not tested in production separately, verified by design / characterization. 6) this value assumes worst case of reading flash line with all cells erased. in case of 50% cells written with ?1? and 50% cells written with ?0?, the maximum current drops down to 95 ma. 7) relevant for the power supply dimens ioning, not for thermal considerations. in case of erase of data flash, internal flash array loading effects may generate transient current spikes of up to 15 ma for maximum 5 ms. 8) no gpio and ebu activity, lvds off 9) this value is relevant for the power supply dimensio ning. the currents caused by the gpio and ebu activity depend on the particular application and should be added separately. if two flash modules are programmed in parallel, the current increase is 2 24 ma. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 149 v1.1, 2009-04 5.3 ac parameters all ac parameters are defin ed with the temperature co mpensation disabled. that means, keeping the pads cons tantly at maximum strength. 5.3.1 testing waveforms figure 22 rise/fall time parameters figure 23 testing wave form, output delay figure 24 testing waveform , output high impedance 10% 90% 10% 90% v ss v ddebu v ddp t r rise_fall t f mct04881_a.vsd v dde / 2 test points v dde / 2 v ss v ddebu v ddp mct04880_new v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 150 v1.1, 2009-04 5.3.2 output rise/fall times table 17 output rise/fall times (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. class a1 pads rise/fall times 1) 1) not all parameters are subject to production test, but verified by design/characterization and test correlation. t ra1 , t fa1 ? ? 50 140 18000 150 550 65000 ns regular (medium) driver, 50 pf regular (medium) driver, 150 pf regular (medium) driver, 20 nf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a2 pads rise/fall times 1) t ra2 , t fa2 ? ? 3.7 7.5 7 18 50 140 18000 150 550 65000 ns strong driver, sharp edge, 50 pf strong driver, sharp edge, 100pf strong driver, med. edge, 50 pf strong driver, soft edge, 50 pf medium driver, 50 pf medium driver, 150 pf medium driver, 20 000 pf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class b pads 3.3v 5% rise/fall times 1) 2) 2) parameter test correlation for v ddebu = 2.5 v 5% t rb , t fb ? ? 3.0 3.7 7.5 ns 35 pf 50 pf 100 pf class b pads 2.5v 5% rise/fall times 1) 3) 3) parameter test correlation for v ddebu = 2.5 v 5% t rb , t fb ? ? 3.7 4.6 9.0 ns 35 pf 50 pf 100 pf class f pads rise/fall times t rf1 , t rf1 ? ? 2 ns lvds mode rise/fall times t rf2 , t rf2 ? ? 60 ns cmos mode, 50 pf www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 151 v1.1, 2009-04 5.3.3 power sequencing figure 25 5 v / 3.3 v / 1.5 v power-up/down sequence the following list of rules applies to the power-up/ down sequence: ? all ground pins v ss must be externally connected to one singl e star point in the system. regarding the dc current component, a ll ground pins are in ternally directly connected. ? at any moment, each power supply must be hi gher than any lo wer_power_supply - 0.5 v, or: vdd5 > vdd3.3 - 0.5 v; vdd5 > vdd1.5 - 0.5 v;vdd3.3 > vdd1.5 - 0.5 v, see figure 25 . ? during power-up and power-down, the volt age difference betwe en the power supply pins of the same voltage (3.3 v, 1.5 v, and 5 v) with different names (for example vddp, vddfl3 ...), that are internally co nnected via diodes, mu st be lower than 100 mv. on the other hand, all power supply pins with the same name (for example power-up 8.vsd 1.5v 3.3v 5v t v +-5% +-5% +-5% t -12% -12% porst 0.5v 0.5v 0.5v v ddp v aref power down power fail www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 152 v1.1, 2009-04 all vddp ), are internally di rectly connected. it is recomme nded that the power pins of the same voltage are driven by a single power supply. ? the porst signal may be de activated after all vdd5, vdd3.3, vdd1.5, and varef power-supplies and the oscillator have reac hed stable operation, within the normal operating conditions. ? at normal power down the porst signal should be activated wi thin the normal operating range, and then the power suppl ies may be switched off. care must be taken that all fl ash write or delete sequen ces have been completed. ? at power fail the porst signal must be activate d at latest when any 3.3 v or 1.5 v power supply voltage falls 12% below the nominal level. the same limit of 3.3 v-12% applies to the 5 v power supply too. if, under t hese conditions, the porst is activated during a flash write, only the memo ry row that was the target of the write at the moment of the power loss will contain unreliable conten t. in order to ensure clean power-down behavior, th e porst signal should be activated as close as possible to the normal operating voltage range. ? in case of a power-loss at any power-supply, all powe r supplies must be powered- down, conforming at the same ti me to the rules number 2 and 4. ? although not necessary, it is additionally recommended t hat all power supplies are powered-up/down together in a controlled wa y, as tight to each other as possible. ? aditionally, regarding the adc reference voltage varef: ? varef must power-up at the same time or later than vddm, and ? varef must power-down eather earlier or at latest to sa tisfy the condition varef < vddm + 0.5 v. this is required in order to prevent discharge of varef filter capacitance through the esd diode s through the vddm power supply. in case of dischargi ng the reference capacitance th rough the esd diodes, the current must be lower than 5 ma. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 153 v1.1, 2009-04 5.3.4 power, pad and reset timing table 18 power, pad and reset timing parameters parameter symbol values unit note / test con dition min. typ. max. min. v ddp voltage to ensure defined pad states 1) 1) this parameter is valid under assumption that porst signal is constantly at low level during the power- up/power-down of the v ddp . v ddppa cc 0.6 ? ? v ? oscillator start-up time 2) 2) t oscs is defined from the moment when v ddosc3 = 3.13 v until the oscillations reac h an amplitude at xtal1 of 0,3 v ddosc3 . this parameter is verified by device characterization. the external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. t oscs cc ? ? 10 ms ? minimum porst active time after power suppli es are stable at operating levels t poa sr 10 ? ? ms ? esr0 pulse width t hd cc program mable 3) 5) 3) any esr0 activation is internally prolonged to scu_rstcntcon.relsa fpi bus clock ( f fpi ) cycles. ? ? f sys ? porst rise time t por sr ? ? 50 ms ? setup time to porst rising edge 4) t pos sr 0 ? ? ns ? hold time from porst rising edge t poh sr 100 ? ? ns testmode trst setup time to esr0 rising edge t hds sr 0 ? ? ns ? hold time from esr0 rising edge t hdh sr 16 1/f sys 5) ? ? ns hwcfg ports inactive after porst reset active 6)7) t pip cc ? ? 150 ns ? ports inactive after esr0 reset active (and for all logic) t pi cc ? ? 8 1/ f sys ns ? power on reset boot time 8) t bp cc ? ? 2.5 ms ? application reset boot time at f cpu =180mhz 9) t b cc 125 ? 575 s ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 154 v1.1, 2009-04 figure 26 power, pad and reset timing 4) applicable for input pins testmode and t rst . 5) f fpi = f cpu /2 6) not subject to production test, verified by design / characterization. 7) this parameter includes the delay of the analog spike filter in the porst pad. 8) the duration of the boot-time is defined between the rising edge of the porst and the moment when the first user instruction has entered t he cpu and its processing starts. 9) the duration of the boot time is defined between the following events: 1. hardware reset: the falling edge of a short esr0 pulse and the moment when the first user instruction has entered the cpu and its processing starts, if the esr0 pulse is shorter than scu_rstcntcon.relsa t fpi . if the esr0 pulse is longer than scu_rstcntcon.relsa t fpi , only the time beyond should be added to the boot time ( esr0 falling edge to first user instruction). 2. software reset: the moment of starting the softwa re reset and the moment when the first user instruction has entered the cpu and its processing starts reset_beh2 as programmed vddp pads pad- state undefined vdd v d d ppa v d d ppa t hd t poa t poa trst testmode esr0 porst t poh hwcfg t hdh t pip t pi tri -state or pull device active t hd t poh t hdh t pip t pi t pip t pi t pi t hdh t pi v ddp -12% v dd -12% www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 155 v1.1, 2009-04 5.3.5 phase locked loop (pll) note: all pll characteristics defined on this and the ne xt page are not subject to production test, but verified by design characterization. phase locked l oop operation when pll operation is enabled and configured, the pll clock f vco (and with it the lmb- bus clock f lmb ) is constantly adjusted to the selected frequency . the pll is constantly adjusting its output frequency to correspond to the input frequency (f rom crystal or clock source), resulting in an accumulated jitter that is limited. this me ans that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. this is especially important for bus cycles using waitstat es and for the operation of timers, serial interfaces, etc. for all slower operations and l onger periods (e.g. pulse train generation or measurement, lo wer baudrates, etc.) the deviat ion caused by the pll jitter is negligible. two formulas are defined fo r the (absolute) approximat e maximum valu e of jitter d m in [ns] dependent on the k2 - factor, the lmb clock frequency f lmb in [mhz], and the number m of consecutive f lmb clock periods. (2) (3) table 19 pll parameters (o perating conditions apply) parameter symbol values unit note / test con dition min. typ. max. accumulated jitter |d m | ? ? 7 ns ? vco frequency range f vco 400 ? 800 mhz ? vco input frequency range f ref 8 ? 16 mhz ? pll base frequency 1) 1) the cpu base frequency with which the application softwa re starts after porst is calculated by dividing the limit values by 16 (this is the k2 factor after reset). f pllbase 50 200 320 mhz ? pll lock-in time t l ? ? 200 s ? for k2 100 () and m f lmb mhz [] () 2 ? () d mns [] 740 k2 f lmb mhz [] --------------- -------------- --------------- -5 + ?? ?? 1001 , k2 ? () m1 ? () 05 , f lmb mhz [] 1 ? -------------- -------------- -------------- -------------- -------- 0 0 1 , k2 + ?? ?? = else d mns [] 740 k2 f lmb mhz [] --------------- ----------------- ------------ -5 + = www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 156 v1.1, 2009-04 with rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by th e k2-factor of the pll. beyond this value of m the maximum accumulated jitter remains at a constant value. furth er, a lower lmb-bus clock frequency f lmb results in a higher abso lute maximum jitter value. figure 27 gives the jitter curves for several k2 / f lmb combinations. figure 27 approximated maximum accu mulated pll jitter for typical lmb- bus clock frequencies f lmb note: the specified pll jitter values are valid if the capacitive load per output pin does not exceed c l = 20 pf with the maximum driver and sharp edge, except the e-ray output pins, which can be loaded with c l = 25 pf. in case of a pplications with many pins with high loads, driver strengths and toggl e rates the sp ecified jitter values could be exceeded. note: the maximum peak-to-peak noise on the pad supply voltag e, measured between v ddosc3 at pin e26 and v ssosc at pin f25, is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. the maximum peak-to peak noise on the pad supply votage, measured between v ddosc at pin f26 and v ssosc at pin f25, is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise 0 0.0 m ns d m 2.0 4.0 6.0 10.0 20 40 60 80 100 120 8.0 o TC1797_pll_jitt_m f lmb = 50 mhz ( k2 = 8) f lmb = 50 mhz ( k2 = 16) f lmb = 150 mhz ( k2 = 4) f lmb = 100 mhz ( k2 = 8) = max. jitter = number of consecutive f lmb periods = k2-divider of pll d m m k2 o 7.0 f lmb = 100 mhz ( k2 = 4) 1.0 f lmb = 180 mhz ( k2 = 4) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 157 v1.1, 2009-04 frequencies above 300 khz. these conditions can be achi eved by appropria te blocking of the supply voltage as near as possible to the supply pins and using pcb supply and ground planes. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 158 v1.1, 2009-04 5.3.6 e-ray phase locked loop (e-ray pll) note: all pll characteristics defined on this and the ne xt page are not subject to production test, but verified by design characterization. note: the specified pll jitter values are valid if the capacitive load per output pin does not exceed c l = 20 pf with the maximum driver and sharp edge, except the e-ray output pins, which can be loaded with c l = 25 pf. in case of a pplications with many pins with high loads, driver strengths and toggl e rates the sp ecified jitter values could be exceeded. note: the maximum peak-to-peak noise on the pad supply voltag e, measured between v ddpf3 at pin g24 and v ssosc at pin f25, is li mited to a peak-to -peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. the maximum peak-to peak noi se on the pad su pply voltage, measured between v ddpf at pin g23 and v ssosc at pin f25, is limited to a peak-to-peak voltage of v pp = 100 mv for noise frequencies below 300 khz and v pp = 40 mv for noise frequencies above 300 khz. these conditions can be achi eved by appropria te blocking of the supply voltage as near as possible to the supply pins and using pcb supply and ground planes. table 20 pll parameters of the syst em pll(operating conditions apply) parameter symbol values unit note / test con dition min. typ. max. accumulated jitter at e_ray module clock input 1) 1) short term jitter and long term jitter for all numbers p of sample clocks (p 1), with f osc = 20mhz, k = 6, and f sample = 80 mhz. d p_eray_i ? ? 0.5 ns ? accumulated jitter at sysclk pin 2) 2) short term jitter and long term jitter for all numbers p of sample clocks (p 1), with f osc = 20mhz, k = 6, and f sample = 80 mhz. d p_eray_e ? ? 0.8 ns ? vco frequency range f vco_eray 400 ? 500 mhz ? vco input frequency range f ref_eray 20 ? 40 mhz ? pll base frequency 3) 3) the cpu base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the k factor after reset). f pllbase_eray 140 ? 320 mhz ? pll lock-in time t l_eray ? ? 200 s ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 159 v1.1, 2009-04 5.3.7 bfclko output clock timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%,; t a = -40 c to +125 c; c l = 35 pf figure 28 bfclko output clock timing table 21 bfclk0 output clock timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. bfclko clock period t bfclko cc 13.33 2) 2) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. ? ? ns ? bfclko high time t 5 cc 3 ? ? ns ? bfclko low time t 6 cc 3 ? ? ns ? bfclko rise time t 7 cc ? ? 3 ns ? bfclko fall time t 8 cc ? ? 3 ns ? bfclko duty cycle t 5 /( t 5 + t 6 ) 3) 3) the pll jitter is not included in this parameter. if the bfclko frequency is equal to f cpu , the k divider has to be regarded. dc 45 50 55 % ? 0.9 v dd mct04883_mod 0.5 v ddp05 bfclko t bfclko t 5 t 6 0.1 v dd t 8 t 7 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 160 v1.1, 2009-04 5.3.8 jtag interface timing the following parameters are applicable for communicatio n through the jtag debug interface. the jtag module is fu lly compliant with ieee1149.1-2000. note: these parameters are not subject to production test but verified by design and/or characterization. table 22 jtag interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. tck clock period t 1 sr 25 ? ? ns ? tck high time t 2 sr 12 ? ? ns ? tck low time t 3 sr 10 ? ? ns ? tck clock rise time t 4 sr ? ? 4 ns ? tck clock fall time t 5 sr ? ? 4 ns ? tdi/tms setup to tck rising edge t 6 sr 6 ? ? ns ? tdi/tms hold after tck rising edge t 7 sr 6 ? ? ns ? tdo valid after tck falling edge 1) (propagation delay) 1) the falling edge on tck is used to generate the tdo timing. t 8 cc ? ? 13 ns c l = 50 pf t 8 cc ? ? 3 ns c l = 20 pf tdo hold after tck falling edge 1) t 18 cc 2 ? ? ns tdo high imped . to valid from tck falling edge 1) 2) 2) the setup time for tdo is given implicitly by the tck cycle time. t 9 cc ? ? 14 ns c l = 50 pf tdo valid to high imped. from tck falling edge 1) t 10 cc ? ? 13.5 ns c l = 50 pf www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 161 v1.1, 2009-04 figure 29 test clock timing (tck) figure 30 jtag timing mc_jtag_tck 0.9 v ddp 0.5 v ddp t 1 t 2 t 3 0.1 v ddp t 5 t 4 t 6 t 7 t 6 t 7 t 9 t 8 t 10 tck tms tdi tdo mc_jtag t 18 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 162 v1.1, 2009-04 5.3.9 dap interface timing the following parameters are applicable for communicat ion through the dap debug interface. note: these parameters are not subject to production test but verified by design and/or characterization. figure 31 test clock timing (dap0) table 23 dap interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dap0 clock period t 11 sr 12.5 ? ? ns ? dap0 high time t 12 sr 4 ? ? ns ? dap0 low time t 13 sr 4 ? ? ns ? dap0 clock rise time t 14 sr ? ? 2 ns ? dap0 clock fall time t 15 sr ? ? 2 ns ? dap1 setup to dap0 rising edge t 16 sr 6 ? ? ns ? dap1 hold after dap0 rising edge t 17 sr 6 ? ? ns ? dap1 valid per dap0 clock period 1) 1) the host has to find a suitable sampling point by analyzing the sync telegram response. t 19 sr 8 ? ? ns 80 mhz, c l = 20 pf t 19 sr 10 ? ? ns 40 mhz, c l = 50 pf mc_dap0 0.9 v ddp 0.5 v ddp t 11 t 12 t 13 0.1 v ddp t 15 t 14 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 163 v1.1, 2009-04 figure 32 dap timing host to device figure 33 dap timing device to host t 16 t 17 dap0 dap1 mc_ dap1_rx dap1 mc_dap1_tx t 11 t 19 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 164 v1.1, 2009-04 5.3.10 ebu timings v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf for address/data; c l = 40pf for the control lines. 5.3.10.1 ebu asynchronous timings for each timing, the accumulated pll jitter of the programed duration in number of clock periods must be added separately . operating condit ions apply and c l = 35 pf. table 24 common timing parame ters for all asy nchronous timings 1) 1) not subject to production test, verified by design/characterization. parameter symbol limit values unit edge setting min max pulse width deviati on from the ideal programmed width due to the a2 pad asymmetry, strong driver mode, rise delay - fall delay. c l = 35 pf. t a cc -1 1.5 ns sharp -2 1 medium ad(31:0) output delay to adv rising edge, multiplexed read / write t 13 cc -5.5 2 ? ad(31:0) output delay t 14 cc -5.5 2 ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 165 v1.1, 2009-04 read timings table 25 asynchronous re ad timings, multiplexed and demultiplexed 1) 1) not subject to production test, verified by design/characterization. parameter symbol limit values unit min max a(23:0) output delay to rd rising edge, deviation from the ideal programmed value. t 0 cc -2.5 2.5 ns a(23:0) output delay t 1 cc -2.5 2.5 cs rising edge t 2 cc -2 2.5 adv rising edge t 3 cc -1.5 4.5 bc rising edge t 4 cc -2.5 2.5 wait input setup t 5 sr 12 ? wait input hold t 6 sr 0 ? data input setup t 7 sr 12 ? data input hold t 8 sr 0 ? mr / w output delay t 9 cc -2.5 1.5 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 166 v1.1, 2009-04 multiplexed read timing figure 34 multiplexed read access new_muxrd_async_10.vsd cs[3:0] cscomb adv rd mr/w ad[31:0] data in bc[3:0] wait a[23:0] valid address next addr. address out t 2 t a t a t a t a t 4 t 5 t 6 t a t 13 t 14 t 7 t 8 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 1 t 0 pv + pv + pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) command delay phase cmddelay 0...7 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 167 v1.1, 2009-04 demultiplexed read timing figure 35 demultiplexed read access new_demuxrd_async_10.vsd cs[3:0] cscomb adv rd mr/w ad[31:0] data in bc[3:0] wait a[23:0] valid address next addr. t 2 t a t a t a t a t 4 t 5 t 6 t a t 7 t 8 t 9 ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 1 t 0 pv + pv + pv + t 3 pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) new addr. phase www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 168 v1.1, 2009-04 write timings table 26 asynchronous write timin gs, multiplexed and demultiplexed 1) 1) not subject to production test, verified by design/characterization. parameter symbol limit values unit min max a(23:0) output delay to rd/ wr rising edge, deviation from the ideal programmed value. t 30 cc -2.5 2.5 ns a(23:0) output delay t 31 cc -2.5 2.5 cs rising edge t 32 cc -2 2 adv rising edge t 33 cc -2 4.5 bc rising edge t 34 cc -2.5 2 wait input setup t 35 sr 12 ? wait input hold t 36 sr 0 ? data output delay t 37 cc -5.5 2 data output delay t 38 cc -5.5 2 mr / w output delay t 39 cc -2.5 1.5 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 169 v1.1, 2009-04 multiplexed write timing figure 36 multiplexed write access new_muxwr_async_10.vsd cs[3:0] cscomb adv ad[31:0] data out bc[3:0] wait a[23:0] valid address next addr. ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 30 t 31 t a t 32 t a t 33 t a t a t a t 34 t 37 t 38 t 39 t 35 t 36 data hold phase pv + pv + pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) datac 0...15 pv + pv + address out t 13 t 14 pv + rd/wr mr/w www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 170 v1.1, 2009-04 demultiplexed write timing figure 37 demultiplexed write access new_demuxwr_async_10.vsd cs[3:0] cscomb adv ad[31:0] data out bc[3:0] wait a[23:0] valid address next addr. ebu state address phase address hold phase (opt.) command phase recovery phase (opt.) new addr. phase addrc aholdc rdwait rdrecovc addrc 1...15 0...15 duration limits in ebu_clk cycles 1...31 0...15 1...15 control bitfield: t 30 t 31 t a t 32 t a t 33 t a t a t a t 34 t 37 t 38 t 39 t 35 t 36 data hold phase pv + pv + pv + pv + pv + pv + pv + pv + pv + pv = programmed value, t ebu_clk * sum (correponding bitfield values) datac 0...15 pv + pv + mr/w rd/wr www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 171 v1.1, 2009-04 5.3.10.2 ebu burst mode access timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf; table 27 ebu burst mode read / write access timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. output delay from bfclko active edge 2) 2) this is a default parameter which are applicable to al l timings which are not explic itly covered by the other parameters. t 10 cc -2 ? 2 ns ? rd and rd/ wr active/inactive after bfclko active edge 3) 3) an active edge can be rising or falling edge, depending on the settings of bits bfcon.ebse / ecse and clock divider ratio. negative minimum values for these parameters mean that the last data read during a burst may be corrupted. however, with clock feedback enabled, this value is oversampling not required for the lmb transaction and will be discarded. t 12 cc -2 ? 2 ns ? cs x output delay from bfclko active edge 3) t 21 cc -2.5 ? 1.5 ns ? adv active/inactive after bfclko active edge 4) 4) this parameter is valid for busconx.ebse = 1 and busapx.extclk = 00 b . for busconx.ebse = 1 and other values of busapx.extcl k, adv and baa will be delayed by 1 / 2 of the lmb bus clock period t cpu = 1 / f cpu . for busconx. ebse = 0 and busapx.extclk = 11 b , add 2 lmb clock periods. for busconx. ebse = 0 and other values of busapx.extclk add 1 lmb clock period. t 22 cc -2 ? 2 ns ? baa active/inactive after bfclko active edge 4) t 22a cc -2.5 ? 1.5 ns ? data setup to bfclki rising edge 5) t 23 sr 3 ? ? ns ? data hold from bfclki rising edge 5) t 24 sr 0 ? ? ns ? wait setup (low or high) to bfclki rising edge 5) t 25 sr 3 ? ? ns ? wait hold (low or high) from bfclki rising edge 5) t 26 sr 0 ? ? ns ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 172 v1.1, 2009-04 figure 38 ebu burst mode re ad / write access timing 5) if the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as at asynchronous access. so t5, t6, t7 and t8 from the asynchronous timings apply. data (addr+4) burstrdwr_4.vsd t 10 bfclki bfclko a[23:0] t 22 adv t 21 address phase(s) command phase(s) burst phase(s) recovery phase(s) next addr. phase(s) t 22 t 21 t 21 burst start address next addr. rd rd/wr d[31:0] (32-bit) wait t 12 t 12 data (addr+0) t 24 baa d[15:0] (16-bit) t 22a burst phase(s) data (addr+2) data (addr+0) t 22a t 10 t 22 t 23 t 24 t 23 1) t 26 t 25 output delays are always referenced to bclko. the reference clock for input characteristics depends on bit ebu_bfcon.fdbken. ebu_bfcon.fdbken = 0: bfclko is the input reference clock. ebu_bfcon.fdbken = 1: bfclki is the input reference clock (ebu clock feedback enabled). 1) cs[3:0] cscomb www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 173 v1.1, 2009-04 5.3.10.3 ebu arbitration signal timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf; figure 39 ebu arbitration signal timing table 28 ebu arbitration signal timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. output delay from bfclko rising edge t 27 cc ? ? 3 ns ? data setup to bfclko falling edge t 28 sr 11 ? ? ns ? data hold from bfclko falling edge t 29 sr 2 ? ? ns ? ebuarb_1 bfclko hlda output breq output t 27 t 27 t 27 t 27 t 29 t 28 t 29 t 28 bfclko hold input hlda input www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 174 v1.1, 2009-04 5.3.11 peripheral timings note: peripheral timing parameters are not subj ect to production te st. they are verified by design/characterization. 5.3.11.1 micro link interface (mli) timing figure 40 mli interface timing t 27 t 25 t 26 t 16 t 17 t 15 t 15 mli_tmg_2.vsd tdatax tvalidx tclkx rdatax rvalidx rclkx treadyx rreadyx t 10 t 13 t 11 t 12 t 14 t 20 t 27 mli transmitter timing mli receiver timing t 23 t 21 t 22 t 24 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 175 v1.1, 2009-04 note: the generation of rreadyx is in th e input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. table 29 mli timings (operating condit ions apply), c l = 50 pf parameter symbol values unit note / test co ndition min. typ. max. mli transmitter timing tclk clock period t 10 cc 2 t mli ? ? ns 1) 1) t mlimin. = t sys = 1/ f sys . when f sys = 90 mhz, t 10 = 22.22 ns and t 20 = 11.11 ns. tclk high time t 11 cc 0.45 t 10 0.5 t 10 0.55 t 10 ns 2)3) 2) the following formula is valid: t 11 + t 12 = t 10 tclk low time t 12 cc 0.45 t 10 0.5 t 10 0.55 t 10 ns 2) 3) tclk rise time t 13 cc ? ? 4) ns ? tclk fall time t 14 cc ? ? 4) ns ? tdata/tvalid output delay time t 15 cc -3 ? 4.4 ns ? tready setup time to tclk rising edge t 16 sr 18 ? ? ns ? tready hold time from tclk rising edge t 17 sr 0 ? ? ns ? mli receiver timing rclk clock period t 20 sr 1 t mli ? ? ns 1) rclk high time t 21 sr ? 0.5 t 20 ? ns 5)6) rclk low time t 22 sr ? 0.5 t 2 0 ? ns 5) 6) rclk rise time t 23 s r ? ? 4 ns 7) rclk fall time t 24 s r ? ? 4 ns 7) rdata/rvalid setup time to rclk falling edge t 25 s r 4.2 ? ? ns ? rdata/rvalid hold time from rclk rising edge t 26 s r 2.2 ? ? ns ? rready output delay time t 27 c c 0 ? 16 ns ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 176 v1.1, 2009-04 3) the min./max. tclk low/high times t 11 / t 12 include the pll jitter of f sys . fractional divider settings must be regarded additionally to t 11 / t 12 . 4) for high-speed mli interface, strong driver sharp or medium edge selection (class a2 pad) is recommended for tclk. 5) the following formula is valid: t 21 + t 22 = t 20 6) the min. and max. value of is parameter can be adjus ted by considering the other receiver timing parameters. 7) the rclk max. input rise/fall times are best case parameters for f sys = 90 mhz. for reduction of emi, slower input signal rise/fall times can be used for longer rclk clock periods. www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 177 v1.1, 2009-04 5.3.11.2 micro second cha nnel (msc) interface timing figure 41 msc interface timing note: the data at sop should be sampled with the falling edge of fclp in the target device. table 30 msc interface timing (operating condit ions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. fclp clock period 1)2) 1) fclp signal rise/f all times are the same as the a2 pads rise/fall times. 2) fclp signal high and low can be minimum 1 t msc . t 40 cc 2 t msc 3) 3) t mscmin = t sys = 1 / f sys . when f sys = 90 mhz, t 40 = 22,2ns ? ? ns ? sop/enx outputs delay from fclp rising edge t 45 cc -10 10 ns ? sdi bit time t 46 cc 8 t msc ? ns ? sdi rise time t 48 sr 100 ns ? sdi fall time t 49 sr 100 ns ? msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 178 v1.1, 2009-04 5.3.11.3 ssc master/slave mode timing table 31 ssc master/slave mode timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. master mode timing sclk clock period t 50 cc 2 t ssc ? ? ns 1)2)3) 1) sclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) sclk signal high and low times can be minimum 1 t ssc . 3) t sscmin = t sys = 1/ f sys . when f sys = 90 mhz, t 50 = 22.2 ns. mtsr/slsox delay from sclk rising edge t 51 cc 0 ? 8 ns ? mrst setup to sclk falling edge t 52 sr 13 ? ? ns 3) mrst hold from sclk falling edge t 53 sr 0 ? ? ns 3) slave mode timing sclk clock period t 54 sr 4 t ssc ? ? ns 1) 3) sclk duty cycle t 55 / t 54 sr 45 ? 55 % ? mtsr setup to sclk latching edge t 56 sr t ssc + 5 ? ? ns 3) 4) 4) fractional divider switched off, ssc internal baud rate generation used. mtsr hold from sclk latching edge t 57 sr t ssc + 5 ? ? ns 3) 4) slsi setup to first sclk shift edge t 58 sr t ssc + 5 ? ? ns 3) slsi hold from last sclk latching edge t 59 sr 7 ? ? ns ? mrst delay from sclk shift edge t 60 cc 0 ? 15 ns ? slsi to valid data on mrst t 61 cc ? ? 12 ns ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 179 v1.1, 2009-04 figure 42 ssc master mode timing figure 43 ssc slave mode timing ssc_tmgmm sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slsox 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slsox is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50 ssc_tmgsm sclk 1) t 55 mtsr 1) t 57 data valid t 56 slsi t 58 1) this timing is based on the following setup: con.ph = con.po = 0. t 54 t 55 t 59 last latching sclk edge first latching sclk edge t 57 data valid t 56 mrst 1) t 60 first shift sclk edge t 60 t 61 www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 180 v1.1, 2009-04 5.3.11.4 e-ray interface timing the timings in this sectio n are valid for the strong / sharp and strong / medium settings of the output drivers, and for both a1 or a2 input pads. the timing parameters are not subject to production test, but verified by design / characterization. table 32 e-ray interface timing (operating conditions apply) , c l = 25 pf parameter symbol limit values unit notes conditions min. typ. max. txda / txdb signal timing at end of frame time span from last bss to fes without the influence of quartz tolerances d10bit_tx 1) 1) pll jitter included. t 60 cc 997.75 ? 1002.25 ns f oscdd = 20mhz; f oscdd = 40mhz; c l = 25 pf (txda, txdb) txd data valid, from f sample flip-flop txd_reg ? txda, txdb, (dtxasym) 2) 3) 2) refers to delays caused by the asymmetries of the output drivers of the digital logic and the gpio pad drivers. quartz tolerance and pll jitter are not included. 3) e-ray txd output drivers have an asymmetry of rising and falling edges of | t f - t r | 1 ns. |t 61 - t 62 | cc ? ? 1.5 ns asymmetrical delay of rising and falling edge (txda, txdb) rxda / rxdb signal timi ng at end of frame time span between last bss and fes that is properly decoded, without influence of quartz tolerances d10bit_rx 1) 4) 5) 4)limits of 966.5 ns and 1046 ns correspond to (30%, 70%) v ddp flexray standard input thresholds. due to different input thresholds of the TC1797, a correcton of -0.5 ns and +0.1 ns has been applied. t 63 sr 966 ? 1046.1 ns f oscdd = 20mhz; f oscdd = 40mhz; c l = 25 pf (txda, txdb) rxd capture by f sample , rxda / rxdb ? sampling flip-flop, (drxasym) 5) |t 64 - t 65 | cc ? ? 3.0 ns asymmetrical delay of rising and falling edge (rxda, rxdb) www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 181 v1.1, 2009-04 figure 44 e-ray timing 5)valid for output slopes of the bus driver of drxslope 5 ns, 20% v ddp to 80% v ddp , according to the fl exray electrical physical laye r specification v2.1 b. for a1 pads, the rise and fall times of the incoming sign al have to satisfy the following inequality: -1.6 ns t f - t r 1.3 ns . txd t 60 0.7 v ddp 0.3 v ddp bss byte start sequence last crc byte fes frame end sequence e-ray_timing_a1 rxd t 63 0.62 v ddp 0.36 v ddp bss byte start sequence last crc byte fes frame end sequence 0.9 v ddp 0.1 v ddp txd t 61 t 62 t sample 0.62 v ddp 0.36 v ddp rxd t 64 t 65 t sample www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 182 v1.1, 2009-04 5.4 package and reliability 5.4.1 package parameters table 33 thermal characte ristics of the package device package r jct 1) 1) the top and bottom thermal resistance s between the case and the ambient ( r tcat , r tcab ) are to be combined with the thermal resistances between the junction and the case given above ( r tjct , r tjcb ), in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tcat , r tcab ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calc ulated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances. r jcb 1) unit note TC1797 p/pg-bga-416-10 4 6 k/w www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 183 v1.1, 2009-04 5.4.2 package outline figure 45 package outlines p/pg-bga-416 -10, plastic (green) ball grid array pg-bga-416-4, -10, -13, -14-po v02 a26 2.5 max. index marking (sharp edge) index marking af1 a1 25 x 1 = 25 25 x 1 = 25 1 1 (1.17) (0.56) 0.1 0.5 m c ?0.1 ?0.63 -0.13 +0.07 a 416x ?0.25 m b c 0.15 c a 0.2 20 0.5 24 0.2 27 0.2 0.5 0.2 27 20 24 b www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 184 v1.1, 2009-04 you can find all of our package s, sorts of packing and others in infi neon internet page. 5.4.3 flash memory parameters the data retention time of the TC1797?s flash memory (i.e. the time after which stored data can still be retr ieved) depends on the number of times the fl ash memory has been erased and programmed. table 34 flash parameters parameter symbol values unit note / test condition min. typ. max. program flash retention time, physical sector 1)2) 1) storage and inactive time included. 2) at average weighted junction temperature t j = 100 o c, or the retention time at average weighted temperature of t j = 110 o c is minimum 10 years, or the retention time at average weighted temperature of t j = 150 o c is minimum 0.7 years. t ret cc 20 ? ? years max. 1000 erase/program cycles program flash retention time logical sector 1) 2) t retl cc 20 ? ? years max. 100 erase/program cycles data flash endurance (64 kb) n e cc 30 000 ? ? cycles max. data retention time 5 years data flash endurance, eeprom emulation (4 16 kb) n e8 cc 120000 ? ? cycles max. data retention time 5 years programming time per page 3) 3) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5 ms. t pr cc ? ? 5 ms ? program flash erase time per 256-kb sector t erp cc ? ? 5 s f cpu = 180 mhz data flash erase time for 2 32-kb sectors t erd cc ? ? 2.5 s f cpu = 180 mhz wake-up time t wu cc ? ? 4000/ f cpu + 180 s ? www.datasheet.co.kr datasheet pdf - http://www..net/
TC1797 electrical parameters data sheet 185 v1.1, 2009-04 5.4.4 quality declarations table 35 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime 1) 1) this lifetime refers only to t he time when the device is powered on. t op ? ? 24000 hours ? 2) 3) 2) for worst-case temperature profile equivalent to: 2000 hours at t j = 150 o c 16000 hours at t j = 125 o c 6000 hours at t j = 110 o c 3) this 30000 hours worst-case temperature profile is also covered: 300 hours at t j = 150 o c 1000 hours at t j = 140 o c 1700 hours at t j = 130 o c 24000 hours at t j = 120 o c 3000 hours at t j = 110 o c esd susceptibility according to human body model (hbm) v hbm ? ? 2000 v conforming to jesd22-a114-b esd susceptibility of the lvds pins v hbm1 ? ? 500 v ? esd susceptibility according to charged device model (cdm) v cdm ? ? 500 v conforming to jesd22-c101-c moisture sensitivity level msl ? ? 3 ? conforming to jedec j-std-020c for 240c www.datasheet.co.kr datasheet pdf - http://www..net/
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